.db file in Synopsys stands for ??

[n968...@sparc19.cc.ncku.edu.tw]

Hi,

a .db file after synthesised stand for what ? Is it a gate-level circuit ?

[Forrest O. Arnold]

In <5f1va1$d...@ccnews.ncku.edu.tw> n968...@sparc19.cc.ncku.edu.tw ()
writes:

>
>
> Hi,
>
> a .db file after synthesised stand for what ? Is it a gate-level
circuit ?
>
>

The .db formatted file is a Synopsys (data base) file. It is your
synthesized design saved in the "db" Synopsys format.

Woody Arnold

[n968...@sparc19.cc.ncku.edu.tw]

Forrest O. Arnold (woo...@ix.netcom.com) wrote:
: In <5f1va1$d...@ccnews.ncku.edu.tw> n968...@sparc19.cc.ncku.edu.tw ()

: Woody Arnold

Could you compare db and gate-level circuit ? Do they be the same ?

Thanks in advances,

Nan-Sheng Huang

[Brian Cheebie Merchant]

In the dying days of the second millennium, n968...@sparc19.cc.ncku.edu.tw

() wrote:
> Could you compare db and gate-level circuit ? Do they be the same ?
>
> Thanks in advances,

The db format is simply a way of storing the information. The file could
be anything, Designware parts, a FSM, a gate-level netlist, anything at any
point in the Synopsys pipeline. You would have to import the file to
synopsys and look at it to know what kind of data it was. Gate-level
netlists coming out of synopsys would usually end in ".v" (verilog), ".vhd"
(VHDL), or ".edif" (EDIF). Although several other formats are available.

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