MaxPlusII & VHDL problems
matteo Santoro
is there anybody practice with Altera's Maxplus II?
I've this problem:
I'm developing a VHDL macro that I'll fit in a FPGA (Flex8000) using the
program MAXPLUSII 8.3.
I've noticed that I cannot define a Procedure in the declarative part
of an Architecture (or a Process) of a STATE MACHINE written in VHDL
language.
The MaxplusII compiler says me
"Subprogram Error: Can't interpret subprogram call"
or
"Unknown problem... (!)"
I have, here, the "IEEE Standard VHDL Language Reference manual" and
the MAXplusII VHDL user's manual, and I don't understand what type of
mystake there is in my netlist... I Think that it is conform with the
IEEE spec.
I would like propose you here the netlist: can you help me?
----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Data Creation 30/6/1999
--Last Modify 30/6/1999
--Type: State Machine
--
--Note
entity chiamataprocedura is port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
input1 : in STD_LOGIC; N_EP : in STD_LOGIC_VECTOR (3
DOWNTO 0);
Output1 : out STD_LOGIC ;
Output2 : out STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end chiamataprocedura;
architecture Behave of chiamataprocedura is
type TIPOSTATO is (S0, S1, S2);
signal STATO : TIPOSTATO;
procedure rst_gst is
begin
output1 <= '0';
output2 <= B"0000";
end procedure rst_gst;
begin
macchina_stato: process (CLK, RESET)
begin
if RESET = '1' then
STATO <= S0;
output1 <= '0';
output2 <= B"0000";
elsif (CLK' event and CLK = '1') then
case stato is
when S0 =>
if (N_EP /= B"0100") then
stato <= S1;
else
stato <= S2;
end if;
when S1 =>
if (input1 = '1') then
stato <= S0;
rst_gst;
else
output1 <= '1';
output2 <= B"0001";
stato <= S2;
end if;
when S2 =>
stato <= S0;
end case;
end if;
end process;
end behave;
------------------------
This is the error that the Compiler tell me:
"Error: Unknown problem in e:\<directory name>
\...\chiamataprocedura.vhd((%DLS-E-NoSuchAttr, Object kind Res_72 does
not have attribute qParent; in GetAttr(qParent).)"
Thanks very much for your help.
---------------------------------
Matteo Santoro
matt...@collector.org
bron...@mclink.it
------------------------------
Stan Zaborowski
>
> I've noticed that I cannot define a Procedure in the declarative part
> of an Architecture (or a Process) of a STATE MACHINE written in VHDL
> language.
>
> The MaxplusII compiler says me
> "Subprogram Error: Can't interpret subprogram call"
>
> architecture Behave of chiamataprocedura is
>
> type TIPOSTATO is (S0, S1, S2);
> signal STATO : TIPOSTATO;
>
> procedure rst_gst is
>
> begin
> output1 <= '0';
> output2 <= B"0000";
> end procedure rst_gst;
>
Hello Matteo,
The relevant law is section 8.3.1 or the '87 LRM or section 8.4.1 of
the '93 LRM and is basically this: A procedure defined outside a
process can only assign to signals that are formal parameters of a
procedure.
You must rewrite your procedure to take the ports as output parameters
of the procedure.
I hope this helps.
Stan
--
Stan Zaborowski (978)436-9911 x133
Chrysalis Symbolic Design, Inc. s...@chrysalis.com
101 Billerica Ave. 5 Billerica Park
N. Billerica, MA 01862
me...@mench.com
wrote in article <377A4325...@rmnet.it>:
> I've noticed that I cannot define a Procedure in the declarative
> part of an Architecture (or a Process) of a STATE MACHINE written in
> VHDL language.
>
> The MaxplusII compiler says me
> "Subprogram Error: Can't interpret subprogram call"
>
>
> "Unknown problem... (!)"
You're either operating outside of their subset or have encountered
a bug.
> ...
> This is the error that the Compiler tell me:
> "Error: Unknown problem in e:\<directory name>
> \...\chiamataprocedura.vhd((%DLS-E-NoSuchAttr, Object kind Res_72 does
> not have attribute qParent; in GetAttr(qParent).)"
The error message is reporting an internal error. The third-party
compiler interface they're using has issued an error (the %DLS-...).
Paul
--
Paul Menchini | me...@mench.com |"The last thing I want to do is
OrCAD | www.orcad.com | spread fear, uncertainty and
P.O. Box 71767 | 919-479-1670[v] | doubt in the users' minds."
Durham, NC 27722-1767 | 919-479-1671[f] | --Don Jones, MS's Y2K Product Mgr
matteo Santoro
Stan Zaborowski wrote:
Stan Zaborowski wrote:
> Hi Matteo,
>
> You wrote:
>
> >
> > I've noticed that I cannot define a Procedure in the declarative part
> > of an Architecture (or a Process) of a STATE MACHINE written in VHDL
> > language.
> >
> > The MaxplusII compiler says me
> > "Subprogram Error: Can't interpret subprogram call"
>
> >
> > architecture Behave of chiamataprocedura is
> >
> > type TIPOSTATO is (S0, S1, S2);
> > signal STATO : TIPOSTATO;
> >
> > procedure rst_gst is
> >
> > begin
> > output1 <= '0';
> > output2 <= B"0000";
> > end procedure rst_gst;
> >
>
> Hello Matteo,
>
> The relevant law is section 8.3.1 or the '87 LRM or section 8.4.1 of
> the '93 LRM and is basically this: A procedure defined outside a
> process can only assign to signals that are formal parameters of a
> procedure.
>
> You must rewrite your procedure to take the ports as output parameters
> of the procedure.
>
> I hope this helps.
I have tried to define this procedure inside the process that uses it.
The compiler tell me the same problem!
thanks for your interest.
Matteo
(P.S. Is possible that the Compiler does not accept procedures without any
formal parameters?... But this is strange. The IEEE ref. man. that I have
does not say anything in that sense...)
matteo
Wang Xiao-yun
matteo Santoro <mat...@rmnet.it> wrote in article
<377B1294...@rmnet.it>...
>
>
> Stan Zaborowski wrote:
>
> I have tried to define this procedure inside the process that uses it.
>
> The compiler tell me the same problem!
>
> thanks for your interest.
>
> Matteo
>
> (P.S. Is possible that the Compiler does not accept procedures without
any
> formal parameters?... But this is strange. The IEEE ref. man. that I have
> does not say anything in that sense...)
>
>
> matteo
>
>
The reason of that strange error message:
"Error: Unknown problem in e:\<directory name>
\...\chiamataprocedura.vhd((%DLS-E-NoSuchAttr, Object kind Res_72 does
not have attribute qParent; in GetAttr(qParent).)"
is because, I think, the subprogram can not recognize the signals. You are
attempting to value the 2 output signals of the entity, but since they are
not in the formal parameter list of the procedure, they can not be
recognized.
I modified the procedure like this:
procedure rst_gst(
signal output1: out std_logic;
signal output2: out std_logic_vector(3 downto 0)
) is
begin
output1 <= '0';
output2 <= B"0000";
end procedure rst_gst;
note, the "ouput" here are completely different from the entity's signals.
I checked the new programe under the MAX+Plus II 9.1. The strange
error message disappeared, instead, a new one came out:
"...signal parameter in a subprogram is not supported."
Then I check the Help. To my surprise, the MAX help says even VHDL'93 does
not support signal parameters.
It's quite strange to me, bercause I'm sure that I've seen some subprgrams
with signal parameters(although I did not check their correctness).
I'll make more study on it.
matteo Santoro
Wang Xiao-yun wrote:
I've tried as you suggested me on my version of MaxPlusII (8.3).
When I try to call the procedure in the program, writing
.......
rst_gst(output1, output2);
........
the compiler says me:
"...UNSUPPORTED FEATURED ERROR; SIGNAL PARAMETER IN A SUBPROGRAM IS NOT
SUPPORTED..."
Obviously if I try to call the procedure in this way
...
rst_gst;
...
The compiler has another error because can't interpretate the procedure call...
mah!
Matteo