PALASM/JEDEC to VHDL conversion?

[Timothy J. Stanley]

This has been cross-posted to comp.lang.verilog.

This is a request for any information about converting either:

AMD PALASM input --> Verilog/VHDL models

or

JEDEC file --> Verilog/VHDL models.

We are doing a board design that will use some programmable logic
devices. In particular, we will be using some of the AMD MACH parts
(multiple 22V16s in 1 chip with internal interconnect capability), and
the usual 22V10 type devices.

AMD supplies a CAD tool called PALASM that is used for schematic entry
and simulation for their MACH devices. We currently have Verilog
models of our CPU chip. We want to convert the PALASM/JEDEC
representations of the various PLDs into Verilog or VHDL
automagically. This would permit single hand-generated
representations of any PLD model, and board simulation could proceed
seamlessly and coherently etc etc.

In Chapter 21 of the Verilog manual, there is an example of converting
some sort of PAL16R8 programmable device .dat file to Verilog. Has
anyone written any similar software verilog/VHDL-model-generator that
could help, or wish to offer an opinion about how to most efficienty
proceed.

Thanks in advance,

Tim Stanley
t...@z.eecs.umich.edu

[Mark Beaubien]

>anyone written any similar software verilog/VHDL-model-generator that
>could help, or wish to offer an opinion about how to most efficienty
>proceed.

We use LAI/Logic Modeling PAL models to map JEDECs into Verilog simulations.
From a Valid schematic you place the Pal down and assign a JEDEC file
property to it. After compilation the simulator (RapidSim or Verilog)
has a model of the Pal. LAI charges $10K/yr subscription for their libraries
so unfortunately this may not be very useful to you, seeing your .edu email
address. They might have a discount for schools. LAI works well and
also works with several different simulators. Good luck.
-Mark
beau...@westford.ccur.com

[Mark Beaubien]

[Jon Mellott]

Agreed. However, note that for academics, the LAI SmartModel libraries are
much more affordable. Instead of $10K/year/seat, they are $1K/year for
a site license. There is an additional $500/year charge if you want the
incrementals (quarterly), and additional manual sets are $100/ea.

The LAI libraries have *lots* of parts. PLDs. Memories. Bit slice/processor
blocks. Whole microprocessors. I'd recommend that all academic Cadence Verilog/
RapidSim users get the LAI libraries. If you want a more detailed opinion
from a non-salesman, feel free to contact me via e-mail.

Jon Mellott
High Speed Digital Architecture Laboratory
University of Florida
(j...@alpha.ee.ufl.edu)