Main problem: your FOR loop doesn't advance simulation time with each
iteration. Your whole simulation completes in 0 ps. Put a WAIT
statement, such as "wait for 20 ns;" before the "end loop;"
A few other comments:
Remove the references to the std_logic_arith and std_logic_unsigned
packages. Those are non-standard packages that came from Synopsys, not
IEEE, and are considered deprecated. Plus, you are not actually using
them anyway.
Because your testbench uses entity instantiation for comparator3bit, you
don't need the component definition for it.
Charles Bailey