-explicit in modelsim
Jamil Khatib
Sometimes VHDL files do not compile if I did not include this option
specially when I use std_logic_vectors comparison.
Thanks
Michael Vincze
illegal construct to be analyzed/elaborated.
The construct is related to the equivalence
operator (i.e.: "=".)
Since VHDL is heavily typed, the equivalence
operator "=" is defined by default. For
example if you define a type as follows:
type my_logic_levels is ('U', '0', '1');
You do not have to define an "=" operator. You
are allowed to compare two my_logic_levels without
having to create any more lines of VHDL text.
In fact it is illegal if you do define the "="
operator (according to the LRM - sorry I can not
cite the specific paragraph.)
Synopsys had distributed modified versions of the
IEEE library to include their own math packages.
These packages had overloaded the "=" operator.
The reason was to allow different, but similar
types, to be compared. In either case, the Synopsys
compilers were such that they did not take the
overloading to be illegal. And since a lot of people
were using Synopsys for synthesis, and ModelSim for
simulation, ModelSim had to bite the bullet and allow
a way to handle overloading the "=" operator. As a
note, when we were evaluating synthesis tools, all
were required to handle Synopsys flavor VHDL source.
This is basically handling of the Synopsys IEEE
packages and the Synopsys pragmas.
I hope the explanation helped. It may not be 100%
technically correct. But it should give you an idea
of the history behind the -explicit switch.
Take a look in the ieee.std_logic_arith and
ieee.std_logic_unsigned packages and you will
see the "=" operator being overloaded.
Best regards,
Michael Vincze
Jamil Khatib <jamilk...@yahoo.com> wrote in message
news:38F5D232...@yahoo.com...
Tristan Gingold
>The -explicit switch is used to allow a specific
>illegal construct to be analyzed/elaborated.
>The construct is related to the equivalence
>operator (i.e.: "=".)
>
>Since VHDL is heavily typed, the equivalence
>operator "=" is defined by default. For
>example if you define a type as follows:
>
> type my_logic_levels is ('U', '0', '1');
>
>You do not have to define an "=" operator. You
>are allowed to compare two my_logic_levels without
>having to create any more lines of VHDL text.
>In fact it is illegal if you do define the "="
>operator (according to the LRM - sorry I can not
>cite the specific paragraph.)
according to lrm 2.3.1:
The declaration of a function whose designator is an operator symbol is used to
overload an operator. The se-quence of characters of the operator symbol must
be one of the operators in the operator classes defined in 7.2.
e...@riverside-machines.com.nospam
wrote:
>You do not have to define an "=" operator. You
>are allowed to compare two my_logic_levels without
>having to create any more lines of VHDL text.
>In fact it is illegal if you do define the "="
>operator (according to the LRM - sorry I can not
>cite the specific paragraph.)
It's not actually illegal - it's just inconvenient. See item (3) of:
http://www.model.com/support/technote/tnsynopsys.html
Evan
me...@mench.com
> The -explicit switch is used to allow a specific illegal construct
> to be analyzed/elaborated. The construct is related to the
> equivalence operator (i.e.: "=".)
> Since VHDL is heavily typed, the equivalence operator "=" is defined
> by default. For example if you define a type as follows:
> type my_logic_levels is ('U', '0', '1');
> You do not have to define an "=" operator. You are allowed to
> compare two my_logic_levels without having to create any more lines
> of VHDL text. In fact it is illegal if you do define the "="
> operator (according to the LRM - sorry I can not cite the specific
> paragraph.)
Michael, good explanation, but one nit--it *is* legal to define your own
"=" in this case--I suspect you're thinking of the "no homographs in
the same declarative region" rule, but there is a single exception
when one of the homographs is the declaration of an implicit operator.
BTW, IIRC, I think that the case you're thinking of is the one that
gets around the clash problems that Synopsys' version of
(not)std_logic_arith has with the operators in std_logic_1164.
Some of the explicit operators in (not)std_logic_arith are homographs
of some of the implicit operators in std_logic_1164, so when you have
a use clause like:
library IEEE;
use IEEE.std_logic_1164.all, IEEE.std_logic_arith.all;
you end up trying to import homographs, which does not work.
IIRC, the "-explicit" switch says "favor the explicit operators (in
(not)std_logic_arith) over the implicit homographs (in
std_logic_1164).
Why (not)std_logic_arith was designed to have this problem in the
first place is left as an excercise for the reader....
Paul
--
Paul Menchini | "Outside of a dog, a book is probably man's
Cadence PCB Design Systems | best friend, and inside of a dog, it's too
me...@mench.com | dark to read."
www.orcad.com | --Groucho Marx
Paul Graham
"=" only for limited types (that is, types which do not implicitly
declare "="). Limited types do not exist in VHDL. This restriction is
removed in Ada-95. Interestingly, overloading "=" in Ada automatically
creates a complementary "/=" operator, with the result that
x /= y == not(x = y)
Paul
me...@mench.com wrote:
>
> On Fri, 14 Apr 2000 03:35:19 GMT, Michael Vincze <vin...@home.com>
> wrote in article <XlwJ4.1235$qF4.1...@news1.rdc2.tx.home.com>:
Paul Graham
operators for type T in package T2, because IMHO this defeats the
purpose of a package, which is to encapsulate types.
On the other hand, favoring explicit declarations over implicit ones has
a certain intuitive appeal.
Paul
me...@mench.com
wrote in article <38F75F17...@cadence.com>:
> It's a bad idea to declare a type T in package P1, then overload
> operators for type T in package T2, because IMHO this defeats the
> purpose of a package, which is to encapsulate types.
Agreed. But, someone did it anyway....
> On the other hand, favoring explicit declarations over implicit ones
> has a certain intuitive appeal.
Agreed. But, that's not the way the language (now) works in this
case. It's easy enough to change, in principle, but the process
should be followed so all know it's coming and all tools work the
same.
Andy Rushton
problem requiring the -explicit switch, because that defines two new
types signed and unsigned and overloads the operators for it in the same
declarative region. It was the (now hopefully obsolete) std_logic_signed
and std_logic_unsigned which had the problem. They defined signed and
unsigned as subtypes of std_logic_vector, then tried to overload the
operators, causing a set of homographs to be defined (not just "="). It
also meant that you could not easily mix signed and unsigned in the same
design unit, since they were both actually std_logic_vectors and had the
same set of operators.
Naff or what? My advice to anyone using those two packages is: "Don't".
The problem with std_logic_arith is that it excessively overloads
arithmetic operators so that just about any expression with two or more
operators in it is ambiguous. And the problem with numeric_std is that
it is inconsistent in its handling of truncation, but that is another
story...
Andy
-- Andy Rushton
-- ECS Department, Southampton University, UK
-- mailto:A.J.R...@ecs.soton.ac.uk
-- http://www.ecs.soton.ac.uk/~ajr1