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Using DLL 90 Degree Phase Shift
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Patrick Loschmidt
Jul 11, 2002, 12:22:30 PM7/11/02
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Mike Hicks wrote:
> I would like (and have tried) to use the clk90 out to keep the 4x and 1x
> (divide by 4) clock edges away from each other.
> I would like (and have tried) to use the clk90 out to keep the 4x and 1x
> (divide by 4) clock edges away from each other.
As far as my experience with Xilinx FPGAs goes, this is not possible
because phase shifted outputs refer to CLK0 and multiples/factors also
refer to this clock.
You could try to feed the 1x or 4x clock into annother DCM to shift it
90 degrees.
Regards,
Patrick
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