Abel to VHDL

[Mustafa Baig]

Hi,
Can ABEL code be converted into VHDL code using some software?

thanks

[Joe Gallegos]

You would profit much if you converted Data I/O(now Synario) ABEL into
VHDL. The
contructs are somewhat similar...Examine www.synario.com , perhaps they
may offer some guidance...I've worked with both ABEL and VHDL... I would
simply recommend converting the ABEL sources to VHDL yourself...

professionally yours,

Joe

[Richard Iachetta]

In article <6vlps1$bt3$1...@mendelevium.btinternet.com>,
mus...@btinternet.com says...

> Hi,
> Can ABEL code be converted into VHDL code using some software?

We did a chip fab'ed by OKI a year or so ago and the design was in ABEL.
Rather than write a general ABEL to VHDL converter, we used the following
procedure. Run the ABEL design through Synario and output a
minimized/optimized design. The output file will be DESIGN_NAME.EQ3.
Then, OKI wrote a EQ3 to VHDL converter which is fairly straightforward
compared to a general ABEL to VHDL converter. There are no high level
constructs in a EQ3 such as state-diagrams, if/then/else, case, when, etc.
Its all just combinatorial equations and registers. All the registers are
D-FlipFlops in the EQ3 file also. So a translation program should be
fairly straightforward. OKI doesn't sell this by the way -- its just a
utility they wrote for our project. It shouldn't be that hard to
duplicate though.

In case you're interested in writing one yourself, here's a start. The
combinatorial equations can be translated with simple text substitution:

= changes to <=
# changes to OR
& changes to AND
! changes to NOT

etc.

Flip-flips are specified in the EQ3 file as:

FFNAME.D = D input signal or expression for FFNAME
FFNAME.C = Clock signal name or expression for FFNAME
FFNAME.AR = Asynchronous reset signal name or expression.
FFNAME.Q = Output of FFNAME

So just make a separate clocked process for each flip-flop using these
parameters.

The only other thing is if an I/O signal can be tri-stated, it will be
specified as:

signame.OE = OE_expression;

Translate this to:

signame <= (signame's equation) when (OE_expression = '1') else 'Z';

Then wrap it all up in the standard VHDL entity/architecture syntax and
you've got it. Hope this helps.

--
Rich Iachetta
iach...@us.ibm.com
I do not speak for IBM.

[Ken Coffman]

You may find this to be interesting reading:

http://www.isdmag.com/ic-logic/ABEL/ABEL.html

Joe Gallegos wrote in message <361FD7...@ibm.net>...

>Mustafa Baig wrote:
>>
>> Hi,
>> Can ABEL code be converted into VHDL code using some software?
>>

[Bertrand]

There is a MUCH easier way to get the "gate level" VHDL out
of Abel : it's just a click away in Synario !
The trick is to add a (even dummy) test bench in your ptoject.
Then new processes are available, especially "VHDL Simulation Model"
when you highlight your Abel module.
This model can be used also as a synthesizeable description.

HOWEVER, I don't recommend this method which is all but
a real "translator".

Example :
when !CLR then Q := Q+1;
in Abel will translate into a bunch of individual feedback
expressions for each D register of Q.

When synthesized back from VHDL, there is no chance
that synthesis can notice it's a counter and infer a very efficient
structure from that...

The RIGHT methode would be to rewrite the Abel code into VHDL :
process(clk)
begin
if clk'event and clk='1' then
if CLR='1' then
Q <= others=>'0';
else
Q <= Q + one;
end if;
end if
end process;
Then the VHDL synthesizer will produce the best results.

Rich gave useful hints on the translation, but you should
be also aware of some specifics of Abel especially how
Abel handles unspecified conditions vs VHDL, like in my
example above ! (when CLR is asserted)

The other major disadvantage of the "gate-level" translation is
maintainability !
What if you need to alter or trim the translated VHDL ?

In summary, the crude Abel -> VHDL method suggested can
be useful for very simple modules resolving to a handful of gates,
but otherwise, high level translation should be considered.

NOTE that if you use Synario, Abel modules can coexist
very optimally within a VHDL project !
This is probably the BEST solution, since the Abel modules
receive an optimal synthesis in this flow, and you can
convert them only if you have to.

Last trick :
if you convert Abel to VHDL by hand, then it's very cool
to get the VHDL translation mentionned and use it only
FOR SIMULATION, to ensure that your translation behaves
like the original module !

Hope it helps,

Bert CUZEAU
ALSE France
alse_place_the_at_sign_here_club-internet.fr
http://ourworld.compuserve.com/homepages/alse

-----Message d'origine-----
De : Richard Iachetta <iach...@us.ibm.com>
Groupes de discussion : comp.lang.vhdl
Date : lundi 12 octobre 1998 21:45
Objet : Re: Abel to VHDL

>In article <6vlps1$bt3$1...@mendelevium.btinternet.com>,
>mus...@btinternet.com says...

>> Hi,
>> Can ABEL code be converted into VHDL code using some software?
>

>We did a chip fab'ed by OKI a year or so ago and the design was in ABEL.

>Rather than write a general ABEL to VHDL converter, we used the following
>procedure. Run the ABEL design through Synario and output a
>minimized/optimized design. The output file will be DESIGN_NAME.EQ3.
>Then, OKI wrote a EQ3 to VHDL converter which is fairly straightforward
>compared to a general ABEL to VHDL converter.

(snip)