VHDL Address Decoder

[Lawrence LaFranier]

I am new to VHDL and I have a question. In the past I have used simple
equations for address decoders with various plds from Lattice, SGS and
AMD. How does one go about doing an address decoder in VHDL for an
Altera device?

Thanks,
Lawrence

[VhdlCohen]

Lawrence

If I understand your question correctly, you're thinking about address decoding
to be used as enables (e,g., load enables).
I have two answers to your question:
1. Generating the Decode outputs:
signal LdEnable : Std_Logic_Vector(3 downto 0); --
..
with Addr(1 downto 0) select
LdEnable <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
2. Unless absolutely necessary (e.g., for IO assignements), the above solution
is low level, and is generally implemented by designers who are migrating from
schematic capture into VHDL. Thus, they tend to use VHDL as a schematic entry
language with decoders and separate muxes. If this is the case, you should be
thinking at a higher level of abstraction, and let the synthesizer do the work.
Thus:
Some_Proc: process
begin
wait until Clk = '1';
case Addr(1 downto 0) is
when "00" =>
S_r <= Data; -- not ld enable for the register S_r;
when "10" =>
S_r <= OtherData; -- no mux control either
...
end case;
end process Some_Proc;

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Ben Cohen vhdl...@aol.com (310) 721-4830
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Author of following textbooks:
VHDL Coding Styles and Methodologies, 2nd Edition,
isbn 0-7923-8474-1 Kluwer Academic Publishers, 1999
VHDL Answers to Frequently Asked Questions, 2nd Edition,
isbn 0-7923-8115-7 Kluwer Academic Publishers, 1998
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