Nested CASE statements?

Kelly Mann

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Apr 27, 1994, 12:52:41 PM4/27/94

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Hi, I'm relatively new to VHDL and I was wondering if it is legal to
have nested CASE/WHEN constructs? My book doesn't seem to say...

Thanks,

Kelly Mann

**********************************************************
Kelly Mann
Electrical Engineering
University of Wisconsin - Madison
**********************************************************

Holger Veit

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Apr 27, 1994, 2:29:04 PM4/27/94

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In article <2pm58p$8...@news.doit.wisc.edu>, ma...@cae.wisc.edu (Kelly Mann) writes:
|> Hi, I'm relatively new to VHDL and I was wondering if it is legal to
|> have nested CASE/WHEN constructs? My book doesn't seem to say...
|>

Nested case statements are allowed, of course. A case statement is a
"sequential statement" and within each alternative, you may have a
sequence of sequential statements. Whether all analyzers and simulators
actually allow unlimited nesting of statements, is however a different
question. They should...

Rich Hatcher

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Apr 27, 1994, 3:27:45 PM4/27/94

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In article 8...@news.doit.wisc.edu, ma...@cae.wisc.edu (Kelly Mann) writes:
>Hi, I'm relatively new to VHDL and I was wondering if it is legal to
>have nested CASE/WHEN constructs? My book doesn't seem to say...

Yes. But here is a suggestion. Anytime you have a question like that
you should write a simple test case and try it. You will learn much
more than if you find the answer in a book or from a friend.

Once you have a test case that fails, but you think it should work,
then is a good time to ask others about it.

This is *NOT* meant to say not to ask for help anytime. Just trying
to help.

Thomas Dettmer

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Apr 28, 1994, 2:58:45 AM4/28/94

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In article <1994Apr27.1...@mksol.dseg.ti.com> hat...@dseg.ti.com writes:
>In article 8...@news.doit.wisc.edu, ma...@cae.wisc.edu (Kelly Mann) writes:
>>Hi, I'm relatively new to VHDL and I was wondering if it is legal to
>>have nested CASE/WHEN constructs? My book doesn't seem to say...
>
>Yes. But here is a suggestion. Anytime you have a question like that
>you should write a simple test case and try it. You will learn much
>more than if you find the answer in a book or from a friend.
>
>Once you have a test case that fails, but you think it should work,
>then is a good time to ask others about it.
>

This is also true in cases where you think, it should not work.
Unfortunately there are still a lot of tools around, that accept non-VHDL
constructs and don't even give you a warning. Be aware of that, especially
if you have to write models for others, possibly using a different toolset.

(This is not opposition to the above: I only want to suggest, that after the
test it might still be usefull to consult a book, friends, this group...at
that time, it will possibly give deeper understanding.)

tom.
--
det...@ls1.informatik.uni-dortmund.de
phone: +49-231 755 6464, FAX: +49-231 755 6555
T. Dettmer, Dortmund University, Computer Science I, 44221 Dortmund, Germany

Electronic Cad Software Account

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Apr 28, 1994, 2:50:14 AM4/28/94

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i think it is better not to.....

Menchini and Associates

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Apr 29, 1994, 10:51:02 AM4/29/94

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In article <2pm58p$8...@news.doit.wisc.edu>,

Kelly Mann <ma...@cae.wisc.edu> wrote:
>Hi, I'm relatively new to VHDL and I was wondering if it is legal to
>have nested CASE/WHEN constructs? My book doesn't seem to say...

Yes it is. Both are sequential statements that contain other sequential
statements.

--Paul