how to see signal in labrary in Simvision?

[bcinepara]

now i do vhdl-verilog mixed simulation. one ip designed vhdle, others
designed verilog incuding testbench
now. i am in the face of problem.
i want to see signals in VHDL RTL File compiled in work labrary. but i
can't see the signals
this is script that i used
---------------------------------------------------------------------------------------------------------------------------------
mkdir WAVE work log
mkdir work/lpm work/altera_mf

# HardMacro library
ncvhdl -v93 -work lpm ./../env/stratixLib/220pack.vhd
ncvhdl -v93 -work lpm ./../env/stratixLib/220model.vhd
ncvhdl -v93 -work altera_mf
./../env/stratixLib/altera_mf_components.vhd
ncvhdl -v93 -work altera_mf ./../env/stratixLib/altera_mf.vhd

# MJPEG Control source
ncvhdl -v93 -logfile ./log/interfaceMem.log \
./../code/memory/stratix_vhdl_memory/dc_syncram64x32.vhd

ncvhdl -v93 ./../code/memory/stratix_vhdl_memory/fifoMem.vhd

ncshell -logfile ./log/fifoMem.ncshell.log \
-import vhdl -into verilog worklib.fifoMem:fifoMem_arch

# MJPEG Encoder Core
ncvhdl -v93 -logfile ./log/mjpegencoder_mem.log \

./../code/mjpegEncoder/mjpegEncIP/stratix_vhdl_memory/dual_syncram16x8.vhd
\

./../code/mjpegEncoder/mjpegEncIP/stratix_vhdl_memory/sync_ram64x16.vhd
\

./../code/mjpegEncoder/mjpegEncIP/stratix_vhdl_memory/sync_ram128x8.vhd
\

./../code/mjpegEncoder/mjpegEncIP/stratix_vhdl_memory/sync_ram256x8.vhd
\

./../code/mjpegEncoder/mjpegEncIP/stratix_vhdl_memory/sync_ram768x8.vhd
# ncvhdl -v93 -logfile ./log/mjpegencoder_rom.log \
#
./../code/mjpegEncoder/mjpegEncIP/stratix_vhdl_memory/HeaderTables_ROM.vhd
ncvhdl -v93 -logfile ./log/mjpegencoder.log \
./../code/mjpegEncoder/mjpegEncIP/std_pack.vhd \
./../code/mjpegEncoder/mjpegEncIP/mth_pack.vhd \
./../code/mjpegEncoder/mjpegEncIP/DualRamBank64x16.vhd \
./../code/mjpegEncoder/mjpegEncIP/DualRamBank768x8.vhd \
./../code/mjpegEncoder/mjpegEncIP/if_fifo.vhd \
./../code/mjpegEncoder/mjpegEncIP/zz_sm.vhd \
./../code/mjpegEncoder/mjpegEncIP/dctshared.vhd \
# ./../code/mjpegEncoder/mjpegEncIP/lutrom2_lpm_rom.vhd \
./../code/mjpegEncoder/mjpegEncIP/lutrom2_lut.vhd \
./../code/mjpegEncoder/mjpegEncIP/quant_ram.vhd \
./../code/mjpegEncoder/mjpegEncIP/dct.vhd \
./../code/mjpegEncoder/mjpegEncIP/quant.vhd \
./../code/mjpegEncoder/mjpegEncIP/mf.vhd \
./../code/mjpegEncoder/mjpegEncIP/add_header.vhd \
./../code/mjpegEncoder/mjpegEncIP/rle.vhd \
./../code/mjpegEncoder/mjpegEncIP/huffmanrom.vhd \
./../code/mjpegEncoder/mjpegEncIP/huffman.vhd \
./../code/mjpegEncoder/mjpegEncIP/entropy.vhd \
./../code/mjpegEncoder/mjpegEncIP/jpg_enc.vhd
ncshell -generic -logfile ./log/mjpegencoder.ncshell.log \
-import vhdl -into verilog
worklib.JPEG_EncoderAndController:Rtl

ncvlog -define "DEBUG_TAB=1" -logfile ./log/coreControl.log \
./../code/FIFO/sc_fifo64x32.v \
./../code/mjpegEncoder/AhbSyncEnc.v \
./../code/mjpegEncoder/loadDataEnc.v \
./../code/mjpegEncoder/saveDataEnc.v \
./../code/mjpegEncoder/EncoderAhbTop.v

# Simulation Model
ncvlog -define "Resolution_64by48=1" \
-define "VideoType422=1" \
-logfile ./log/simModel.log \
./../env/AHB_simmodel4Encoder.v \
./../env/MC_simmodel4Encoder.v

# testbench
ncvlog -define "Resolution_64by48=1" \
-define "VideoType422=1" \
-logfile ./log/testBench.log \
./../env/tb_MJPEGEncoder.v

ncelab -libverbose -logfile ./log/ncelab.log \
-access +rwc \
-status \
-timescale 1ns/10ps \
worklib.tb:module

ncsim -nowarn "ASSERT" \
worklib.tb:module |tee simulationRpt.log
---------------------------------------------------------------------------------------------------------------------------------
and i used dump command in verilog testbench

initial begin
$shm_open("./WAVE/shm0"); $shm_probe("AMC"); #( 60*1000*1000);
$shm_close();
$shm_open("./WAVE/shm1"); $shm_probe("AMC"); #( 60*1000*1000);
$shm_close();
$shm_open("./WAVE/shm2"); $shm_probe("AMC"); #( 60*1000*1000);
$shm_close();
$shm_open("./WAVE/shm3"); $shm_probe("AMC"); #( 60*1000*1000);
$shm_close();
end

now i want to see component signals in altera_mf labrary but, i can't
see the signals

[Ajeetha]

Hi,
I've not used it in the way you showed - i.e. with $shm_probe in
code, however with TCL I had great success in dumping mixed HDL signals
with hardly any issues. Try:

ncsim top_cfg -tcl -input dump.tcl

--- dump.tcl having -----
database -open -shm -default
probe -create -shm / -depth all -all
run
exit
----

HTH
Ajeetha, CVC
www.noveldv.com

P.S. It has been a while since Ised NC, hence the TCL commands may be
wrong, take a look at "cdsdoc" for exact commands.