Altera AHDL to VHDL/Verilog conversion

[Zeev Yelin]

I am working on a proposal to convert a design project (involving some Flex7k
devices) from Altera AHDL to Verilog/VHDL, RTL mainly.
can anybody share experience or point to tools/text processing scripts that
do it?
Thanks in advance
Zeev

[Leo Shvarberg]

Hi,
One way to do it is to enable a VHDL(or Verilog) output writer in
Max II +. The resuting code will be purely structural, but it can be
imported into any VHDL simulators. I have used this approcach with
Model tech simulator. It worked fine.
Good Luck.
Leo.