Rising and falling edge
H.L
I have an entity that includes 2 processes. One process has in the
sensitivity list a clock (lets say clock_1) while the other one has another
clock (lets say clock_2). The first process makes use the rising edge of
clock_1 while the latter uses the falling edge of clock_2. Is this thing
legal or am I going to meet problems during synthesis? In the simulation
everything is right...
Harris
Theron Hicks (Terry)
"H.L" wrote:
Harris,
I can speak from experience (at least with Xilinx FPGAs). This should
synthesize quite easily. The CLBs in the various Xilinx parts have
programmable edge settings (i.e. rising or falling edge). If I recall
correctly, both flipflops in any CLB will require the same edge, but the edge
is programmable for each CLB independently. In my case I had to have a serial
communications system where the clock frequency was set to have odd number bits
clocked in on the negative edge and even number bits clocked in on the positive
edge. I just used 2 separate processes and the interleaved the resultant
data. It works great, at least in simulation. The hardware is not yet
finished.
Theron Hicks
Tim Hubberstey
Whether or not you have problems depends on the target technology for
your synthesis. If you're targetting an FPGA that has selectable clock
polarities you should be OK. I answered this question a couple weeks ago
so I'll just paste my previous answer (ignore any stuff not relevant
here) in here...
... It is, however, quite possible that the device library you're
mapping to does not include negative edge FFs. For instance, many simple
PLDs only have a positive edge clock input. If the FFs aren't in the
library, the only way the synthesizer can create them is to add an
inverter to the clock input of a positive edge FF, if this is even
possible (the routing resources to do this may not even exist). This is
generally a "bad thing" because you lose the tight skew control that
comes from a dedicated clock tree. Further, if you are creating an ASIC,
the use of negative edge FFs may be disallowed by your vendor because
they can't be incorporated into scan chains for production testing.
Also, other primitives in the device (RAMs, shift registers, etc.) may
not be available with negative edge trigger.
It is therefore best to use only positive edge FFs unless you're sure
you can tolerate the reduction in code portability as well as the other
device, tool, and vendor issues.
If you really need negative edge FFs and your device
library/synthesizer/scan generator doesn't support them, you can create
an inverted clock net to drive positive edge FFs. This adds another
clock domain to your design and may have other problems associated with
it but it generally works.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
H.L
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