The problem is syncronization, and slight differences in propigation
time for each bit of the counter.
This can cause the faster counter, when sampled by the slower clock,
when it is counting from a value like 0111 to the value 1000 to see
some of the new bits and some of the old bits, allowing ANY value
between 0000 and 1111 to appear.
One simple solution is to change the counters to "Gray Counters" which
only change a single bit on each transisition, counting like:
000
001
010
011
111
110
100
101
100
000
And that sort of value won't get grabled crossing the clock domain.