How can I design Galois field 2^m multiplier.

[lokesh kumar]

Hi,

I am new to VHDL design. I want to design Galois field 2^m multiplier. First I want to start with Galois field 4 bit multiplier then 8 bit and then m bit multiplier. So please help me out with it.Any suggestion will be helpful.

[Rob Doyle]

I don't know how FPGAs do it... but in software most Galois field
multipliers exponentiate the two terms and then add them.

Exponentiation is a simple lookup table.

Rob.

[kevin....@xilinx.com]

Do you mean the size of the field is 2^m, i.e. you want to build a multiplier over GF{2^m}? And are you talking about a constant multiplier (i.e., multiplying r*k, where k is a constant)? Probably; this is the type used in something like a Reed-Solomon encoder. If this is what you are doing there is a simple matrix operation you can use which synthesizes to a bunch of XORs. I forget the exact matrix but I found it in Petersen's book, which is nice concise manual.

[kevin....@xilinx.com]

I meant Peter Sweeney's book, not Petersen's. Here's that matrix. I don't know if it will format properly in this font. This multiplies an input number b (beta) in the polynomial basis by alpha to the ith power, where i is constant. Beta is a J-bit row vector, where the field is GF{2**J}, and the matrix is JxJ bits. The multiplications are over GF{2}. I hope this makes sense. There's an example in Sweeney. You'll need to make a table of the powers of alpha first so you can populate the matrix.

b*(a**i) =
[ a**(i+J-1) ]
[ ... ]
b*[ a**(i+1) ]
[ a**i ]

[lokesh kumar]

Could you please help me to design a code from an algorithm? I found the algorithm but it is a bit confusing for me to design the code as I am new to it.It would be a great help if you have a look on the algorithm and try to help me out with it.Please provide my your email and I can send you the algorithm.

Thank you

[JK]

http://en.wikipedia.org/wiki/Linear_feedback_shift_register#Galois_LFSRs

[Daniel Kho]

There's a Galois LFSR project in OpenCores:
http://www.opencores.org/project,galois_lfsr

It's a simple design, which gives you the ability to "configure" the taps of the LFSR easily. The design will automatically generate the LFSR structure with all the XOR gates accordingly based on the taps you chose (see user.vhdl).

E.g.:
tapVector:boolean_vector:=(
0|1|2|8=>true, 7 downto 3=>false
)

Disclosure: I'm the author of the project, so may have a bias towards it.

[Dio Gratia]

On Saturday, June 22, 2013 4:10:25 AM UTC+12, lkp wrote:
> Any suggestion will be helpful.

There's a gate level representation of a GF(2M) parallel Galois Field multipler in expired patent US 4,918,638, which you can find by googling.

In theory a person having ordinary skill in the art is capable of implementing the claimed invention found in a patent.

The gate level representation should make it fairly easy to translate into a behavioral representation in VHDL. It looks like it could synthesis pretty compactly as long as you kept it in one process.

[sara...@gmail.com]

HI sir/madam

i m doing the project in galois field multiplier.I want to design Galois field 2^m multiplier. I want to start with Galois field 8 bit and then m bit multiplier. So please help me.

[surf...@gmail.com]

On Friday, 21 June 2013 18:10:25 UTC+2, lkp wrote:
> Hi,
>
> I am new to VHDL design. I want to design Galois field 2^m multiplier. First I want to start with Galois field 4 bit multiplier then 8 bit and then m bit multiplier. So please help me out with it.Any suggestion will be helpful.

here you can find an example
https://surf-vhdl.com/how-to-implement-galois-multiplier-in-vhdl/

[gnuarm.del...@gmail.com]

You are about five years too late...

Rick C.