Monitoring with exact timing (Comparison Verilog/VHDL)

[Patrick Chouraqui]

Hi,

I am using VSS, and read from a sdf file the delay values of my cell.
Then, I am doing monitoring on my cell on a set of vectors using
"monitor event *'signal"

I am also using Verilog XL of Cadence to do the same with the lines:
" initial
begin
$monitor( $realtime , "\t \q = %b , \j = %b , \k =
%b ,
\cp = %b , \s = %b , \si = %b ,", \q , \j , \k , \cp , \s ,
\si );
end
"

As output, I get the changes of signal and the time of the change.
My problem is that both simulators round the timing value, but in an
other side, eg,
if in my sdf file I have delay=0.168, for verilog the change is done
after 0.17 ns, and
for VHDL after 0.16 ns.

How could I impose both simulator to give me the exact value of the time
without
rounding.

Thank you for your help,

Patrick

[Hyuk Jae Lee]

In Cadence Verilog-XL, $monitor system task function displays
$realtime variable with time units and time scales governed by
`timescale compiler directive.

For example, If the $readtime variable has 0.168ns
`timescale 1ns/10ps gives you 0.17ns.

I propose you to test the test module below,

`timescale 1ns/100ps
module test;
reg sig;
paramter p = 1.55;
initial begin
$monitor($readtime, ,"sig=%b",sig);
#p sig = 0;
#p sig = 1;
end
endmodule

Then substitute the compiler directive with `timescale 1ns/10ps
and compare it.

Hyuk

Patrick Chouraqui 이(가) <35890525...@chipx.co.il> 메시지에서
작성하였습니다...

[Ulrich Reichert HL DC PE MC 5 Tel. 089/636-23367]

Hi,

to avoid the rounding you have to use a timescale command:

$timeformat (-12,0," ps",0);

This command sets the maximum accuracy for the $time and $realtime varibles.
In this example it is set to pico seconds (-12), for nano seconds it would
be -9 and so on. The string ' ps' appears after the time value, if you dont
want it use "". If there are multiple timeformat commands, the last one is
valid. For more information see e.g. the cadence documentation.

regards

Ulrich

[purnacha...@gmail.com]

Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

[rickman]

On 2/3/2016 9:35 AM, purnacha...@gmail.com wrote:
> Hai everyone,
>
> i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

[purnacha...@gmail.com]

thanks for the answer but the assert will use for the result which we are not expecting. But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Purna

[Nicolas Matringe]

Use a process:

monitor : process(monitored_signal)
begin
report "monitored_signal has changed" severity note;
end process monitor;

I think messages are time-stamped by he simulator. In case they're not,
adding a time stamp to the message is left as an exercise.

Nicolas

[rickman]

On 2/3/2016 5:35 PM, purnacha...@gmail.com wrote:
> On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
>> On 2/3/2016 9:35 AM, purnacha...@gmail.com wrote:
>>> Hai everyone,
>>>
>>> i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.
>>
>> You can try the assert command. When the assertion is not true it can
>> print a report that typically includes a time stamp by the simulator.
>> No need to actually code up the time I believe.
>>
>> --
>>
>> Rick
>
> thanks for the answer but the assert will use for the result which we are not expecting.

I don't know what you mean by "the assert will use for the result which
we are not expecting". If you mean the assert statement is for errors,
that is not true. It does not care what you put in the assert statement.
You can use "assert not signal_name'event report "signal changed"
severity NOTE" to give a report each time the signal changes. "signal
changed" is anything you wish to report, but I think the time is
reported always.

> But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Rather than ask me to learn Verilog, how about you let me show you how
to use VHDL? Then you can do what you want with VHDL. Asking people to
spoon feed you is not a good way to get help.

--

Rick

[purnacha...@gmail.com]

sorry Rick, i don't mean that way.... i tried using the assert but i am getting the other results what i am not expecting. so i asked you in that way... i will try again, thanks for the response

Purna

[rickman]

Nicolas gives you a another answer and actually gives code. He skips
the assert part of the statement and only uses the report although it
has to be used in a process since report alone is only a sequential
statement. Assert is either sequential or concurrent so can be used in
a process or an architecture.

With the example I provided you should get a report every time the
signal changes. What are you seeing?

--

Rick

[purnacha...@gmail.com]

> Nicolas gives you a another answer and actually gives code. He skips
> the assert part of the statement and only uses the report although it
> has to be used in a process since report alone is only a sequential
> statement. Assert is either sequential or concurrent so can be used in
> a process or an architecture.
>
> With the example I provided you should get a report every time the
> signal changes. What are you seeing?
>
> --
>
> Rick

Rick, Thank you very much for the suggestions. Finally i achieved what i want to implement.

[rickman]

Glad it worked out.

--

Rick