IEEE/GSCOMP library question - using vt library

[Kartik Vaidyanathan]

Hi,

I am using the vt library to do synthesis and P&R for those of you
familiar with the library.

Synthesis : using Ambit Buildgates

generated the .tlf file and performed synthesis on my verilog description
to generate a .vg synthesized netlist.

Now i want to simulate my netlist to verify the synthesis. The library has
two more .vhd files

vtvtlib25_FTGS.vhd
vtvtlib25_components.vhd that have the actual description of all the cells
in the library. So i have to ncvhdl them during my verification.

The ncvhdl fails giving me these errors.....use
IEEE.GS_TYPES.sdt_values_t;
|
ncvhdl_p: *E,SELLIB (./source/vtvtlib25_components.vhd,22|8): unit
(GS_TYPES) not found in library (IEEE).

library GSCOMP;
|
ncvhdl_p: *E,LIBNOM (./source/vtvtlib25_FTGS.vhd,55|13): logical library
name must be mapped to design library [11.2].

There are several more errors.....for missing libraries......
QUESTIONS:
Where are the libraries, GSCOMP, IEEE_ASIC, IEEE.GS_TYPES ?

I checked version of IEEE libraries we use , DID not find them?

Is it Synopsys specific because i found reference to these libraries in a
Synopsys manual?

Anyways to get them? workaround this problem?

Anyone else used the vt library ?

Thanks
Kartik

[Andre Powell]

Hi Kartik,
You can dump out the design from Ambit in VHDL using the
write_vhdl
commmand, you should also use the hierarachiacal switch ie

write_vhdl -hier

You can also define what (VHDL) library calls you would like included in the
net list by using a set_global
command, I don't have an AMBIT reference at hand but if you have a look at
the command reference it should become
clear.

I have never used any form of TLF output so I can't comment. I haven't got
round to simulating a Verilog Netlist but I've done
lots of VHDL net lists. The two files that you mention are directed at a
VHDL net list. You will need to compile these to a specified library, I
suspect the FTGS file contains the cell descriptions in VHDL and the
component file contains a package containing the component declarations for
the cells (so you don't have to declare each one each time you use it).

However if you want to stick with the Verilog route then you will need to
contact your vendor for the appropriate Verilog
gate descriptions.

Hope that helps.

Best Regards

Andre'
"Kartik Vaidyanathan" <vaid...@egr.msu.edu> wrote in message
news:b3nmlk$2ia7$1...@msunews.cl.msu.edu...

[Kartik Vaidyanathan]

Hi Andy

Thanks for that info.....here is what i did now

1. Genrated the vhdl netlist using
write_vhdl -hier netlist.vhd

Instead of using including the library in Ambit to simplify things i put
them in the same lib and compiled them.....should be the same.
2. I then decide to ncvhdl my simulation vhd files before i ncvhdl my vhdl
netlist so that the components there can read their architecture.
vtvtlib25_FTGS.vhd
vtvtlib25_components.vhd

THESE HAVE EXACTLY what you thgt they did in your reply. If i ncvhdl this
TECHNICALLY i should not get errors cos these are the vendor lib. However
i end up with these errors

use IEEE.GS_TYPES.sdt_values_t;

|
ncvhdl_p: *E,SELLIB (./source/vtvtlib25_components.vhd,22|8): unit
(GS_TYPES) not found in library (IEEE).

library IEEE_ASIC;
|
ncvhdl_p: *E,LIBNOM (./source/vtvtlib25_FTGS.vhd,47|16): logical library

name must be mapped to design library [11.2].

library GSCOMP;
|
ncvhdl_p: *E,LIBNOM (./source/vtvtlib25_FTGS.vhd,55|13): logical library
name must be mapped to design library [11.2].

THIS IS WHERE I HAVE MY MAIN PROBLEM. WHAT ARE THESE LIBRARIES, IEEE
STANDARD SHOULD HAVE ASIC, what is GSCOMP. My IEEE libraries and SYNOPSYS
libraries that are common to both vhdl/verilog......dont have these basic
lib for these files to compile. If i can compile the above files i think i
wont have any problem with the netlist.

Am i on the correct path or do u think i am still not doing something
correctly?

3.. Now inspite of above errors i go ahead simulate the netlist
ncvhdl netlist.vhd

as expected have errors
component and2_1 is
|
ncvhdl_p: *E,OPCOIS (./source/vtcounter.vhd,29|21): Optional keyword IS
isonly
allowed in 93. end component and2_1;

architecture netlist of counter is
|
ncvhdl_p: *E,ENNOFN (./source/vtcounter.vhd,20|30): Intermediate file for
entity
'COUNTER' could not be loaded, entity may require re-analysis

Any IDEAS....where i can find info on those two libraries?

ONE MORE Q: what do u use instead of the TLF file.......lib/db?

Thanks in advance
Kartik

"Andre Powell" <andre....@ntlworld.com> wrote in message
news:YIJ7a.7498$EN3....@newsfep4-glfd.server.ntli.net...

[Andre Powell]

Hi Kartik,
Hmmm, I don't have a copy of Modelsim here or any other way to look at the
IEEE stuff. However
as you say the vendor libraries should compile. Also I'm not really aware of
your simulation flow, what exactly
is
ncvhdl
?
I really think you should have a look at your vendor documentation or
contact them as I think this is the only way that
you are going to solve this one. Sorry I can't be of any more help, it won't
be the first time that there has been a bug in
a vendor library, I can remember a library whose flip flop didn't flip flop.

Best Regards

Andre'
"Kartik Vaidyanathan" <vaid...@egr.msu.edu> wrote in message

news:b3nu8r$2piv$1...@msunews.cl.msu.edu...

[Andre Powell]

Hi Kartik,
I have been doing some hunting around (isn't Google fantastic !). OK it
looks like FTGS is something
regarding the Synopsys libraries and is dedicated to creating various
libraries.
If you have a look at this location

http://www2.informatik.uni-jena.de/~doersing/lehre/ps/sn99.10_dok/library/lc
rm2/lcrm2_c.pdf

then it you will see the package that is being referred to. However I have a
feeling that you are using the wrong files
for your gate level simulation. Ask to see if your vendor will provide you
with specifically VITAL compliant cell Libraries or
the Verilog cell libraries if you want to stick to Verilog.

Hope that helps

Andre'
"Kartik Vaidyanathan" <vaid...@egr.msu.edu> wrote in message

news:b3nu8r$2piv$1...@msunews.cl.msu.edu...

[Kartik Vaidyanathan]

Hi Andy

Thanks for the info. ncvhdl is the Cadence compiler for vhdl.

Kartik
"Andre Powell" <andre....@ntlworld.com> wrote in message

news:FeM7a.7643$EN3....@newsfep4-glfd.server.ntli.net...

[Srinivasan Venkataramanan]

Hi Kartik,

"Kartik Vaidyanathan" <vaid...@egr.msu.edu> wrote in message

news:b3nu8r$2piv$1...@msunews.cl.msu.edu...
> Hi Andy
>
<SNIP>

> 2. I then decide to ncvhdl my simulation vhd files before i ncvhdl my vhdl
> netlist so that the components there can read their architecture.
> vtvtlib25_FTGS.vhd
> vtvtlib25_components.vhd
>
> THESE HAVE EXACTLY what you thgt they did in your reply. If i ncvhdl this
> TECHNICALLY i should not get errors cos these are the vendor lib. However
> i end up with these errors
>
> use IEEE.GS_TYPES.sdt_values_t;

I am not aware of this VT library, but the above package named GS_TYPES is
NOT a STANDARD IEEE one (FYI the syntax of use is use <lib>.<package>.<all |
specifc type, component etc>.

So it is highly advisable not to use such stuff.

Having said that, I tried looking into the Synopsys installation tree here,
and found that there is a gs_types.vhd file under

$SYNOPSYS/packages/IEEE/src

So try looking for it under AMBIT tree, you should be able to locate it.

(Honestly I haven't done much of VHDL Netlist sims, so can only help you
from VHDL's perspective.)

Once you get hold of that, you have 2 options:

1.> Change the reference to IEEE.GS_TYPES in file vtvtlib25_components.vhd
to VTLIB.GS_TYPES (or some thing like that). Define this VTLIB in your
cds.lib file and compile the GS_TYPES package to that VTLIB.

2.> Make a local IEEE library and point your cds.lib to this local IEEE dir.
This would also mean that you need to compile the original standard stuff
into your local IEEE lib (See $CDS_INST_DIR/tools/inca/files/IEEE.src dir -
where CDS_INST_DIR is your Cadence Installation Dir).

(I personally wouldn't recommend the second option).

> library IEEE_ASIC;
> |
> ncvhdl_p: *E,LIBNOM (./source/vtvtlib25_FTGS.vhd,47|16): logical library
> name must be mapped to design library [11.2].>
> library GSCOMP;
> |
> ncvhdl_p: *E,LIBNOM (./source/vtvtlib25_FTGS.vhd,55|13): logical library
> name must be mapped to design library [11.2].
>

Again, this should be provided by Ambit (or library vendor). I found a
similar one @ $SYNOPSYS/packages dir.

> THIS IS WHERE I HAVE MY MAIN PROBLEM. WHAT ARE THESE LIBRARIES, IEEE
> STANDARD SHOULD HAVE ASIC, what is GSCOMP. My IEEE libraries and SYNOPSYS
> libraries that are common to both vhdl/verilog......dont have these basic
> lib for these files to compile. If i can compile the above files i think i
> wont have any problem with the netlist.
>
> Am i on the correct path or do u think i am still not doing something
> correctly?
>
> 3.. Now inspite of above errors i go ahead simulate the netlist
> ncvhdl netlist.vhd
>

NO, you can't do that. Try getting the above steps pass. Let me know if
you need more help with NC here.

Good Luck.
Srinivasan

>
>

--
Srinivasan Venkataramanan
Senior Verification Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India

http://www.noveldv.com

I don't speak for Intel