SystemVerilog vs SystemC?
saljdf
circuits in plain old Verilog (1995) RTL for several years now.
I've read bits and pieces about SystemC and SystemVerilog,
'revolutionary' HDLs with higher-level constructs for
supposedly better SOC (system-on-chip) complexity projects,
both for verification (simulation) and design description.
I've tried to get a grasp on the relative strengths and
weaknesses of SystemC vs SystemVerilog, but so far I've
only found scattered anecdotes.
I know that EDA tool-support for both is currently very
limited. But what are the prospects for both? Although
VHDL and Verilog co-existed, I'm guessing only one
systemHDL (SystemVerilog, SystemC) will eventually win out
over the other...
Anyone?
Alexander Gnusin
Hi,
Here is my personal opinion about this.
The following symbolic chart presents comparison of Verilog 1995,
System Verilog and SystemC, as I see it now:
Low Level High
Level
Verilog 1995 --------------------------
System Verilog ---------------------------------------
SystemC -------------------------------------
So, System Verilog, while preserving all backward compatibility to the
"old" verilog, targets high level modeling as well.
SystemC, although it has some synthesis support, may still have very
limited usage in RTL design - all of us prefer to take stable, safe
and well-known way, which is Verilog. However, SystemC targets mostly
High-Level Verification needs, and for this task it is a superset of
SystemVerilog.
There is also known overlap between SystemVerilog and SystemC.
IMHO, SystemVerilog is preferable approach, because:
- Everything is done in one language:
- no need for interfaces between the "language" domains - the
whole verification environment becomes simpler
- Eventually, better tool support - no problems with races between
language domains, "all-in-one" waveform & debugging tools etc
- No need to keep an experts for multiple languages - increases
reusability.
However, the final choise must be dictated by verification needs. If
Verification needs require lots of complex High-Level modeling,
SystemC may be a good choice, complementing (but not replacing)
Verilog or SystemVerilog.
I would be also interested to hear another opinions on this topic.
Regards,
Alexander
Swapnajit Mittra
It seems your question has two parts:
- What are the various features of SystemVerilog (SV) and
SystemC (SC)?
- Which one of SV and SC will win 'the race'?
I will attempt to answer the first.
As always, the best place to start to learn about a new
language/language extension is the LRM of that language.
SV version 3.0 LRM is available from Accellera website for free.
http://www.accellera.org/SystemVerilog_3.0_LRM.pdf
SV version 3.1 work is almost complete and the LRM is expected
to be released during DAC this year.
SC version 2.0.1 is available from
http://www.systemc.org/docman2/ViewCategory.php?group_id=4&category_id=32
--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/
K W
> I know that EDA tool-support for both is currently very
> limited. But what are the prospects for both? Although
> VHDL and Verilog co-existed, I'm guessing only one
> systemHDL (SystemVerilog, SystemC) will eventually win out
> over the other...
Given that most EDA tools don't support Verilog 200x yet, I think
"eventually" is going to be a very distant point in the future. Hopefully by
then someone will have come up with a better HDL, one that actually solves
some of the problems of hardware design, rather than trying to bolt on
features from a language that has so many well known issues. Possibly the
semantics of SystemVerilog are tighter, but HDLs are just playing catch up
to 40 y/o languages. There has to be a better way.
Cheers,
JonB
Tom Hawkins
Now there is a better way!
http://www.launchbird.com/products.html
Confluence solves many of today's design problems. It's a language
designed by hardware engineers, for hardware engineers.
Sorry, I couldn't resist this shameless plug. :-)
Regards,
Tom
--
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
to...@launchbird.com
http://www.launchbird.com/
Elf
As for the else clause...I think its there coz well..isnt it supposed
to be good design style to have and else statement with ifs. I mean,
an if without an else could lead to a latch, wont it ? And I guess,
self assignment is used for want of anything better to assign, or coz
the designer dint want to alter the value in the "else" case.
Elf.
David Pursley
I agree with most of what Alexander said... except for some of his
conclusions...
I completely agree with the "graphic" showing a comparison of Verilog,
SystemVerilog, and SystemC. I also agree that the SystemVerilog and
SystemC overlap at RTL, and that there is little reason to move to
SystemC simply to do RTL design.
However, there are two more reasons that would dictate a move to
SystemC.
In Alexander's post, he mentioned that your verification may need
"lots of complex High-Level modeling." In fact, the same can be true
of your design. In the past, there was no way to synthesize a complex
high-level design, so moving the algorithm (whether written in C or as
a paper specification) to RTL was a necessity. Today, you can
synthesize high-level designs, so manual creation of RTL is no longer
necessary.
Second, we've seen maybe people looking at SystemC precisely for a
"single-language" solution... the same reason for which Alexander
concluded SystemVerilog is the language of choice. The difference, of
course, is in perspective. From the electonic system level (ESL),
which includes both hardware and software, SystemC is a single
language solution.
I'm also interested in other opinions (supporting or dissenting).
With best regards,
-Dave
===================
David Pursley
Forte Design Systems (http://www.ForteDS.com)
al...@ottawa.com (Alexander Gnusin) wrote in message news:<a504dc86.03052...@posting.google.com>...
> Hi,
> Here is my personal opinion about this.
> The following symbolic chart presents comparison of Verilog 1995,
> System Verilog and SystemC, as I see it now:
>
> Low Level High
> Level
> Verilog 1995 --------------------------
> System Verilog ---------------------------------------
> SystemC -------------------------------------
>
> There is also known overlap between SystemVerilog and SystemC.
> IMHO, SystemVerilog is preferable approach, because:
> - Everything is done in one language:
> - no need for interfaces between the "language" domains - the
> whole verification environment becomes simpler
> - Eventually, better tool support - no problems with races between
> language domains, "all-in-one" waveform & debugging tools etc
> - No need to keep an experts for multiple languages - increases
> reusability.
> <--- snip --->