ALTERA GDF to VHDL QUESTION
Asher C. Martin
I am doing some undergraduate research this summer at Beckman Institute
and I am working on some VHDL code to control an analog to digital
converter for various sensors on a robot.
I am fairly new to ALTERA's MAX+PLUS II software and have a question
regarding how to convert GDF files to straight VHDL. I would like to
know if it is possible to tern a GDF file into a VHDL file.
Any suggestions...?
Best regards,
>Asher<
(Undergraduate students @ UIUC)
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Asher C. Martin
805 West Oregon Street
Urbana, IL 61801-3825
(217) 367-3877
E-MAIL: mar...@acm.uiuc.edu
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Jaya Rajesh
VHDL files, I'm using Orcad Capture for creating the top level block
diagram and VHDL file.
Regards,
Jaya Rajesh.
Rickman
>
> I don't think it is possible with altera maxplusII. After finishing the
> VHDL files, I'm using Orcad Capture for creating the top level block
> diagram and VHDL file.
>
> Regards,
> Jaya Rajesh.
Jaya,
You are the first person I have heard from who is designing an FPGA
using Orcad and VHDL. I attempted this a year ago using version 7.1. The
software worked so poorly and Orcad support was so unhelpful that I
finally gave up and bought the Xilinx Foundation package to finish the
design.
How far have you gotten? Are you using the new release 9 software or the
older version 7? Are you having any problems with the VHDL synthesis and
simulation?
I liked the fact that I could do a VHDL simulation of my entire design
including the schematic portions. I didn't like the fact that I couldn't
simulate anything because the simulator would crash every third time I
ran it.
--
Rick Collins
rick.c...@XYarius.com
remove the XY to email me.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design
Arius
4 King Ave
Frederick, MD 21701-3110
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301-682-7666 FAX
Internet URL http://www.arius.com
me...@mench.com
<spamgo...@yahoo.com> wrote in article
<377BB5F3...@yahoo.com>:
> Jaya Rajesh wrote:
>> I don't think it is possible with altera maxplusII. After finishing the
>> VHDL files, I'm using Orcad Capture for creating the top level block
>> diagram and VHDL file.
>
>
> How far have you gotten? Are you using the new release 9 software or
> the older version 7? Are you having any problems with the VHDL
> synthesis and simulation?
I'd be interested in hearing, too....
> I liked the fact that I could do a VHDL simulation of my entire
> design including the schematic portions. I didn't like the fact that
> I couldn't simulate anything because the simulator would crash every
> third time I ran it.
Well, if I do say so myself, version 9 is *much* better when it comes
to both performance, compliance, and lack of bugs than 7.1.
Rick, I hope you'll try again when you next need to simulate including
schematics. Try the free demo version on the web page whenever you're
ready.
Paul
--
Paul Menchini | me...@mench.com |"The last thing I want to do is
OrCAD | www.orcad.com | spread fear, uncertainty and
P.O. Box 71767 | 919-479-1670[v] | doubt in the users' minds."
Durham, NC 27722-1767 | 919-479-1671[f] | --Don Jones, MS's Y2K Product Mgr
Rickman
> > design including the schematic portions. I didn't like the fact that
> > I couldn't simulate anything because the simulator would crash every
> > third time I ran it.
>
> Well, if I do say so myself, version 9 is *much* better when it comes
> to both performance, compliance, and lack of bugs than 7.1.
>
> Rick, I hope you'll try again when you next need to simulate including
> schematics. Try the free demo version on the web page whenever you're
> ready.
>
> Paul
I don't have any current plans to eval ver 9. I have the software
sitting on my shelf, but the software was only part of the problem. No
small part of my complaints with Orcad have to do with my $100 phone
bill from calling support and not getting good answers. My experience is
that Orcad doesn't or can't do a good job of supporting FGPA design
because that is not their main business and they just don't know enough
about the issues and techniques involved in FPGA design using an HDL.
I am not trying to slam Orcad, nor do I wish to start an online
argument. But this was my experience.
At this time I am evaluating the Lucent tools for designing their parts.
If this does not pan out, I may be willing to give Orcad another shot.
me...@mench.com
wrote in article <377BDEE4...@yahoo.com>:
> I don't have any current plans to eval ver 9. I have the software
> sitting on my shelf, but the software was only part of the
> problem. No small part of my complaints with Orcad have to do with
> my $100 phone bill from calling support and not getting good
> answers. My experience is that Orcad doesn't or can't do a good job
> of supporting FGPA design because that is not their main business
> and they just don't know enough about the issues and techniques
> involved in FPGA design using an HDL.
>
> I am not trying to slam Orcad, nor do I wish to start an online
> argument. But this was my experience.
Rick, thanks for your feedback. I'm not trying to shill, or to start
an on-line argument, either.
I appreciate your honesty,
Jaya Rajesh
Rickman wrote:
> Jaya Rajesh wrote:
> >
> > I don't think it is possible with altera maxplusII. After finishing the
> > VHDL files, I'm using Orcad Capture for creating the top level block
> > diagram and VHDL file.
> >
> > Regards,
> > Jaya Rajesh.
>
> Jaya,
>
> You are the first person I have heard from who is designing an FPGA
> using Orcad and VHDL.
Rick,
I'm not designing an FPGA using Orcad. Orcad is used just for creating a top
level DSN file equivalent to altera GDF. (If I have the vhdl files, it is
easy to make a dsn in Orcad.). It creates a VHDL netlist so that I dont have
to type the componets and ports.(Actually that is the only step I'm gaining
and that was Asher's question I guess!) I have Orcad (version 9) in my PC for
Schematic Cpature.
Also, I'm not using ORcad for synthesis or simulation.(I don't think it's a
good idea! ) .I have Synplify and Modelsim for that.
Regards,
Jaya Rajesh.
> I attempted this a year ago using version 7.1. The
> software worked so poorly and Orcad support was so unhelpful that I
> finally gave up and bought the Xilinx Foundation package to finish the
> design.
>
> How far have you gotten? Are you using the new release 9 software or the
> older version 7? Are you having any problems with the VHDL synthesis and
> simulation?
>
> I liked the fact that I could do a VHDL simulation of my entire design
> including the schematic portions. I didn't like the fact that I couldn't
> simulate anything because the simulator would crash every third time I
> ran it.
>
Mark Grindell
message that you are expecting something like that.
The general procedure with something like this is to write your VHDL in
sections which reflect your GDF in its most general form. You would create
components where you have separate GDFs and basically create a VHDL
hierarchy in parallel to your GDF structure.
This is the easy bit, just fill in the "component is" and "architecture is"
declarations withthe signals you find in the GDF.
Then you have to work out how each GDF works, and try to express this in
VHDL using clauses which don't involve a clock at all (combinatorial
blocks), or blocks which execute on a clock edge.
The code I would write would involve condition statements, such as if, or
case, and so forth, determining the state of each signal at a time. That way
you can separate the whole circuit into signals and their sources.
This is made a lot easier if you really understand the GDFs, maybe having
worked with them for a bit. Of course, in VHDL, you can comment the thing
far more effectively.
If the design has a lot of flip flops with asynchronous inputs used heavily,
you would probably be advised to use one process per flip flop (or set of
flip flops if they all implement a bus), since the sensitivity list should
contain the clocks and asynchronous controls. I think this is certainly the
best way of doing it in Max Plus II.
Good luck
Mark
Asher C. Martin <mar...@acm.uiuc.edu> wrote in message
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