Test process behaviour

[Peter]

Hi,

I have used VHDL for some years but still get confused sometimes...

I have a testbench with a process calling a number of procedures. Each
procedure represents a test case. One procedure is supposed to inject
a fault by forcing a line low to see if fault flags are set in the
design. The problem is that this procedure mess up all remaining test
even if it is not called from the main process!? The SCL line goes U
when the bus_error_test1 is declared. But not called....

procedure bus_error_test1 is
begin
scl <= '0'; -- Fault injection
Write(SLVADR,"00011011");
....
end bus_error_test1;
...

begin -- Start of main process

Reset;
check_default_reg; -- A number of different tests
ram_test;
ic_tx1; -- All of them report errors because of
the not called procedure
.....

ic_rxtx3;
ic_rx;
--bus_error_test1; -- Procedure made as comment, but still
mess up remaining tests

I am sure You VHDL gurus can explain this behaviour. Its like a
software subroutine that executes despite its not called?? :-)

Regards Peter

[Allan Herriman]

The process has a driver for that signal if any of its procedures makes
an assignment to the signal. The process drives the leftmost value,
which is 'U', until another value is given, but since you never call the
procedure that gives it a value, it stays at 'U'.

Fix: put an assignment in at the first line of the process:

SCL <= 'Z';

Regards,
Allan

[Peter]

> Allan- Dölj citerad text -
>
> - Visa citerad text -

Clever...

Thanks a lot!

Regards Peter