How to 'port map' from std_logic_vector to std_ulogic_vector ...
TO_Hon_Sun
I tried to do "port mapping" from one component which has an
output pin with std_logic_vector type to another component which has an
input pin with std_ulogic_vector type. At the port mapping section in
my VHDL code, I have to map pin by pin, e.g. a(0)=>b(0), a(1)=>b(1) and
so on, otherwise, I won't compile successfully. If it happens for a
std_logic_vector(255 downto 0), it will become a nightmare to me. Is
there any short cut or workaround in order to minimize the work for wide
bus? Thank you very much for anyone who can help on this issue!
Mark
Srinivasan Venkataramanan
Use the conversion functions "To_StdLogicVector" and "To_StdULogicVector"
from IEEE.STD_LOGIC_1164
Package.
For inputs you should convert the "actuals" while for outputs you should
convert the "formals" - I guess
that's understandable too.
Hope this helps.
Regards,
Srini
-- Small example
library ieee;
use ieee.std_logic_1164.all;
-- library ncvhdl_lib;
entity port_map is
end entity port_map;
architecture rtl of port_map is
COMPONENT comp IS
PORT ( a : in std_ulogic_vector(3 downto 0);
b : out std_ulogic_vector(3 downto 0)
);
END COMPONENT comp;
signal a,b,c : std_logic_vector(3 downto 0) ;
begin
u1_comp : comp port map(a=> To_StdULogicVector(a), To_StdLogicVector(b) =>
b );
end architecture rtl;
--
Srinivasan V
IC Design Engineer,
Philips Semiconductors, Eindhoven,
The Netherlands
TO_Hon_Sun <hs...@ezmsgp.hl.siemens.de> wrote in message
news:38E9C372...@ezmsgp.hl.siemens.de...
Jean-Paul GOGLIO
Srinivasan Venkataramanan a écrit dans le message ...
>Hi,
> Use the conversion functions "To_StdLogicVector" and "To_StdULogicVector"
>from IEEE.STD_LOGIC_1164
> Package.
>
>For inputs you should convert the "actuals" while for outputs you should
>convert the "formals" - I guess
> that's understandable too.
>
>Hope this helps.
>
>Regards,
>Srini
And for inout what sould you do ? (maybe it's a stupid question)
J-P GOGLIO
GETRIS S.A.
13 Chemin des Prés
38240 Meylan
Tel : (33) 4 76 18 52 10
E-mail : gog...@getris.com
Fax : (33) 4 76 18 52 01
Srinivasan Venkataramanan
Jean-Paul GOGLIO <gog...@getris.com> wrote in message
news:8cclqg$41m$1...@reader1.fr.uu.net...
>
> Srinivasan Venkataramanan a écrit dans le message ...
> >Hi,
> > Use the conversion functions "To_StdLogicVector" and
"To_StdULogicVector"
> >from IEEE.STD_LOGIC_1164
> > Package.
> >
> >For inputs you should convert the "actuals" while for outputs you should
> >convert the "formals" - I guess
> > that's understandable too.
> >
> >Hope this helps.
> >
> >Regards,
> >Srini
>
>
> And for inout what sould you do ? (maybe it's a stupid question)
>
To be honest I didn't know the answer before you came up with this
question, Thanks :-) I just thought about it
and it seemed to me that you should do the "type convesrion" on both the
sides of port map.
i.e.
u1_comp : comp port map(a=> To_StdULogicVector(a), To_StdLogicVector(b) =>
To_StdULogicVector(b) );
(provided your "b" is an inout port).
I just referred to my "golden reference" i.e. Ben Cohen's VHDL Book (Page
no: 164), he has
given a detailed table for this issue. I also read that in VHDL'93 it is
also possible to do an "explicit type
conversion" during port mapping - no need of any function calls!
Hope this helps,
Srini
>
>
Jean-Paul GOGLIO
Srinivasan Venkataramanan wrote in message ...
> To be honest I didn't know the answer before you came up with this
>question, Thanks :-) I just thought about it
> and it seemed to me that you should do the "type convesrion" on both the
>sides of port map.
>
>i.e.
>
>u1_comp : comp port map(a=> To_StdULogicVector(a), To_StdLogicVector(b) =>
>To_StdULogicVector(b) );
>
>(provided your "b" is an inout port).
>
>I just referred to my "golden reference" i.e. Ben Cohen's VHDL Book (Page
>no: 164), he has
> given a detailed table for this issue. I also read that in VHDL'93 it is
>also possible to do an "explicit type
> conversion" during port mapping - no need of any function calls!
>
>Hope this helps,
>Srini
Fine, until now, i believed that it was not possible, I will try your code,
thanks.
Paul Butler
Srinivasan Venkataramanan <venkataraman...@philips.com> wrote in
message news:FsHoJ...@natlab.research.philips.com...
> Hi,
> Use the conversion functions "To_StdLogicVector" and
"To_StdULogicVector"
> from IEEE.STD_LOGIC_1164
> Package.
How do these conversions compare to the "free" conversions for "closely
related types"?
(LRM '93 7.3.5)
Paul Butler
e...@riverside-machines.com.nospam
The type conversion is fine for '93. However, in '87, type conversions
weren't allowed in port association lists, although the use of
conversion functions was allowed. In other words, to_std(u)logicvector
is portable across '87 and '93, and a type conversion isn't.
I'm pretty sure that DC still doesn't allow a type conversion here
(FPGA Express 3.3 certainly doesn't).
Evan
me...@mench.com
wrote in article <38eb98b8...@news.dial.pipex.com>:
> On Wed, 5 Apr 2000 08:52:27 -0500, "Paul Butler"
> <c_paul...@yahoo.com> wrote:
>>Srinivasan Venkataramanan <venkataraman...@philips.com> wrote in
>>message news:FsHoJ...@natlab.research.philips.com...
>>> Hi,
>>> Use the conversion functions "To_StdLogicVector" and
>>"To_StdULogicVector"
>>> from IEEE.STD_LOGIC_1164
>>> Package.
>>
>>How do these conversions compare to the "free" conversions for "closely
>>related types"?
>>(LRM '93 7.3.5)
> The type conversion is fine for '93. However, in '87, type
> conversions weren't allowed in port association lists, although the
> use of conversion functions was allowed. In other words,
> to_std(u)logicvector is portable across '87 and '93, and a type
> conversion isn't.
However, even in '87, the conversion functions must return constrained
subtypes, so these functions aren't useful for conversion in a port
map....
P
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