How to include Xilinx library for both ModelSim and Synplify?

[Barry Brown]

I need to use some Xilinx primitives in my VHDL, and they seem to be in
different libraries for use with ModelSim and Synplify. Here's what I have
so far...

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- synthesis translate_off
library unisim;
use unisim.all;
-- synthesis translate_on
library virtex;
use virtex.components.all;
...

This works fine in Synplify, but for ModelSim I have to comment out the two
lines...

--library virtex;
--use virtex.components.all;

Does anyone know a better way to "hide" these from ModelSim?

Thanks,
Barry Brown

[Ray Andraka]

you don't need those two lines for synplify either. Just leave them out.

Barry Brown wrote:

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

[Barry Brown]

Ray -
Really? Perhaps I'm missing something then. When the two lines are
commented out, Synplify gives me a warning:

@W: Fifo.vhd(31): Unbound component RAMB4_S4_S4 mapped to black box

I thought that sounded bad, but do you mean I can just ignore it?
I tried it, and the Xilinx P&R works fine, so I guess all is right with the
world. So then what does Synplify include that Virtex library for?

Thanks,
Barry

"Ray Andraka" <r...@andraka.com> wrote in message
news:3D62B4D4...@andraka.com...

[Ken McElvain]

Some components are simple and a component declaration is enough. Some
require a bit more information to interpret, which is stored as
attributes in the package. This might include information used in
DRC checking such as which pins are tristate. If you want to
instantiate a LUT4 then you will need the package. The package
file lives at .../synplify/lib/xilinx/virtex.vhd

In your case nothing more is needed and your component declaration
is all you need.

- Ken

[Ray Andraka]

The xilinx software looks for the edifs for any black boxes in the netlist.
Any that are primitives are already known by xilinx, so they go through the
tools jsut fine. You can avoid the Synplicity nastygrams by putting the
syn_black_box attribute on any primitive components. I never figured out why
synplicity has their own virtex library. It conflicts with unisim, and
requires a special compile in order to simulate it. FWIW, I was stumped by the
same problem when I started out with synplify many maintenance payments ago.

[Ray Andraka]

Ken,

You can also instantiate LUT4's the same way, provided you put a user attribute
(INIT=) on it and add a pragma'd out generic for the init for simulation.

[Ken McElvain]

That is partially true. If you do it the way I suggested, then Synplify
will have a proper timing model for the LUT instead of treating it like
an unknown black box. In both cases, Synplify will not modify the
LUT, but the correct timing model will lead to improved timing of paths
through the LUT.

[Ray Andraka]

OK, that makes sense. Since, in most of our stuff we are very aware of how it is
being constructed (and design the logic for single level as much as possible), it is
not an issue. As I recall, the unisim and the synplicity virtex libraries cannot
co-exist in the same architecture-entity without configuration statements, so if you
use components out of one, you need to use that for all.

[Patrick Loschmidt]

Hi!

> I need to use some Xilinx primitives in my VHDL, and they seem to be in
> different libraries for use with ModelSim and Synplify. Here's what I have
> so far...

I always used

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--pragma translate_off
library UNISIM;
use UNISIM.vcomponents.all;
--pragma translate_on

...

As far as I remember this worked for both programs.

Regards,
Patrick

[Ray Andraka]

And it is portable to another synthesis tool ;-)

Patrick Loschmidt wrote:

--

[Jeff Cunningham]

> This works fine in Synplify, but for ModelSim I have to comment out the
two
> lines...
>
> --library virtex;
> --use virtex.components.all;
>
> Does anyone know a better way to "hide" these from ModelSim?

Create a package called virtexdummy that is just an empty shell:

package components is
-- empty
end components;

Within modelsim compile virtexdummy into a library called "dummy". Use the
library mapping tools to map the name virtex to library "dummy". Now
modelsim will have something to map the library name to and will not
complain and you don't have to comment stuff in/out when going from
synthesis to simulation.

Back when I was using Synplicity, I had to do the same thing with the
library "unisim" when synthesizing.

JC

[ham...@cloud.net.au]

In comp.arch.fpga Jeff Cunningham <j...@sover.net> wrote:
> Within modelsim compile virtexdummy into a library called "dummy". Use the
> library mapping tools to map the name virtex to library "dummy". Now
> modelsim will have something to map the library name to and will not
> complain and you don't have to comment stuff in/out when going from
> synthesis to simulation.
>
> Back when I was using Synplicity, I had to do the same thing with the
> library "unisim" when synthesizing.

It's safe (and useful) to synthesize unisim_vcomp.vhd - no need for
tricks or the Synplify virtex library.

Hamish
--
Hamish Moffatt VK3SB <ham...@debian.org> <ham...@cloud.net.au>