I know this is not really a question about vhdl, but can
somebody explain the differences between flipflops and latches.
Is a latch a flipflop or is a flipflop a latch?
Is a flipflop always triggered by clock-events and a latch not?
Thanks,
Joachim
> Is a latch a flipflop or is a flipflop a latch?
No, they are different (although they are quite similar)
> Is a flipflop always triggered by clock-events and a latch not?
Right. That's exactly (as far as I know) the difference.
As long as the Latch Enable input remains active, the output will follow
the D input. When LE goes inactive, D latches its last state.
On a FF, the output can only change on a clock transition.
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Thus, for a latch, as long as the clock (latch enable) is held in its
active state, Q follows D. A latch holds the value at D, on Q, when LE
goes to an inactive state. With a flip flop, it is the active edge on
clock that cases the value on D to be applied to Q. Thus, the output of
a flip flop only changes right after the occurace of the active edge on
clock.
Both a latch and a flip flop are storage elements (retain their value).
Hope this hepls.
PJ
In article <38A171E3...@mchp.siemens.de>,
Joachim Schmid <Joachim...@mchp.siemens.de> wrote:
> Hello,
>
> I know this is not really a question about vhdl, but can
> somebody explain the differences between flipflops and latches.
>
> Is a latch a flipflop or is a flipflop a latch?
> Is a flipflop always triggered by clock-events and a latch not?
>
> Thanks,
> Joachim
>
Sent via Deja.com http://www.deja.com/
Before you buy.
When a latch has a D input and a Q output, and the Latch Enable is active,
the Q output will follow the D input. When the LE is inactive, the data is
latched. This is a Transparent latch.
Clyde
As you can see from the diverse answers you are getting, sometimes the
term latch is used rather loosely. Clyde is not splitting hairs--a
latch isn't necessarily a clocked object. I have never heard an
unclocked latch called a flip flop. A latch can be, but is not
necessarily asynchronous. I think a flip flop is always clocked. I
don't think your question is unrelated to VHDL since a common
phenomenon in VHDL is the infamous "inferred latch" where the compiler
makes a latch of a signal that the user may have intended to be purely
combinatorial--but that's another subject. Some of the replies have
mentioned D flip flops and D transparent latches. Both latches and
flip flops can also be 2-input objects. For example: Set and Reset
are the inputs to an object and Q and QBar are the outputs. When set
is true and Reset false, Q goes true and QBar false. The outputs remain
in this state (even if Set goes false) until Reset is true (and Set
false) then Q and QBar change states. This is a Set-Reset latch. If
you add a clock input, and specify that the outputs require a specific
clock transition as well as Set or Reset in order to change state, then
you have a Set-Reset flip flop.
Charles
In synthesis a latch is smaller and less power consuming than a Flip-flop.
So for advanced low power design, the use of latches instead of flip-flop is
recommended. Aldough you have to take care signals allways change on the
right moments in time... In other words, FF can't allways just been
exchanged by latches.
Johan Van Dyck
johan.v...@philips.com
Joachim Schmid <Joachim...@mchp.siemens.de> wrote in message
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