('EVENT AND '1') vs. rising_edge()
john_...@optilink.dsccc.com
Hi, everyone, I'm wondering in VHDL, there seems to be 2 ways to implement
detection of rising clks:
1. IF (clk'EVENT) AND (clk = '1') THEN
2. IF rising_edge(clk) THEN
What is the difference in them if my VHDL supports rising_edge()?
Are they actually the same? If not, which is better to use?
thanks,
--john
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Robert H. Klenke
In fact, the rising_edge() function is implemented with the
(clk'EVENT) AND (clk = '1') syntax, so they should be exactly the
same.
Bob
--
-------------------------------------------------------------------------
Bob Klenke, Ph.D., Principal Scientist Dept. of Electrical Engineering
University of Virginia
http://csis.ee.virginia.edu/~rhk2j Charlottesville, VA 22903-2442
-------------------------------------------------------------------------
Andreas Gieriet
john_...@optilink.dsccc.com wrote:
>
> Hi, everyone, I'm wondering in VHDL, there seems to be 2 ways to
> implement detection of rising clks:
> 1. IF (clk'EVENT) AND (clk = '1') THEN
> 2. IF rising_edge(clk) THEN
>
> What is the difference in them if my VHDL supports rising_edge()?
> Are they actually the same? If not, which is better to use?
From s practical point of view, it's *almost* the same.
Assuming, you are talking about std_logic_1164, the rising_edge()
function is defined to be true *only* if the value before the event
was '0' or 'L' and the current value of this event is '1' or 'H';
any other combination is *not* a rising edge in this definition.
For a clock, this has typically only an impact at initialization time.
-- test case for rising_edge()
library ieee;
use ieee.std_logic_1164.all;
entity test is
end test;
architecture test_arch of test is
signal clk1: std_logic := '0';
signal clk2: std_logic := '1';
signal clk3: std_logic; -- 'U'
signal clk4: std_logic; -- 'U'
begin
clk1 <= transport not clk1 after tclk/2;
clk2 <= transport not clk2 after tclk/2;
-- clk3 process
process
begin
-- starts with '0' (last value = 'U')
clk3 <= transport '0', '1' after tclk/2;
wait for tclk;
end process;
-- clk4 process
process
begin
-- starts with '1' (last value = 'U')
-- is this a rising edge?
clk4 <= transport '1', '0' after tclk/2;
wait for tclk;
end process;
-- sensitive process: check
process (clk1, clk2, clk3, clk4)
begin
-- no diff
if clk1'event and clk1='1' then
assert rising_edge(clk1) report "clk1: difference!";
end if;
-- no diff
if clk2'event and clk2='1' then
assert rising_edge(clk2) report "clk2: difference!";
end if;
-- no diff
if clk3'event and clk3='1' then
assert rising_edge(clk3) report "clk3: difference!";
end if;
-- this should be an error according to the ieee definition
if clk4'event and clk4='1' then
assert rising_edge(clk4) report "clk4: difference!";
end if;
end process;
end test_arch;
--
Andreas Gieriet
(Please replace "nospam" by "pobox" in the return address,
which has been altered to foil junk mail senders)
Rick Collins
john_...@optilink.dsccc.com wrote:
> Hi, everyone, I'm wondering in VHDL, there seems to be 2 ways to implement
> detection of rising clks:
> 1. IF (clk'EVENT) AND (clk = '1') THEN
> 2. IF rising_edge(clk) THEN
>
> What is the difference in them if my VHDL supports rising_edge()?
> Are they actually the same? If not, which is better to use?
>
> thanks,
> --john
I just finished reading about this. The rising_edge(clk) will only detect a
change from a low to a high. The clk'event and clk='1' will detect a change to
the '1' state from ANY other state. This includes high impedance, the unknown
state and even a 'H' (weak one) state.
Rick Collins
Hans Lindkvist
john_...@optilink.dsccc.com wrote:
>
> Hi, everyone, I'm wondering in VHDL, there seems to be 2 ways to implement
> detection of rising clks:
> 1. IF (clk'EVENT) AND (clk = '1') THEN
> 2. IF rising_edge(clk) THEN
>
> What is the difference in them if my VHDL supports rising_edge()?
> Are they actually the same? If not, which is better to use?
>
> thanks,
> --john
>
> http://www.dejanews.com/ Now offering spam-free web-based newsreading
rising_edge and falling_edge is not supported by Synopsys for synthesis.
--
Regards
Hans Lindkvist
Robert H. Klenke
>>
>> In article <6dpe3q$fhg$1...@murdoch.acc.Virginia.EDU> you wrote:
>> : In article <6dn1on$fin$1...@nnrp1.dejanews.com>, john_...@optilink.dsccc.com
>> : writes:
>> : |> Hi, everyone, I'm wondering in VHDL, there seems to be 2 ways to
>> : |> implement detection of rising clks:
>> : |> 1. IF (clk'EVENT) AND (clk = '1') THEN
>> : |> 2. IF rising_edge(clk) THEN
>> : |>
>> : |> What is the difference in them if my VHDL supports rising_edge()?
>> : |> Are they actually the same? If not, which is better to use?
>>
>> : (clk'EVENT) AND (clk = '1') syntax, so they should be exactly the
>> : same.
>>
>> Actually, if we're speaking of the rising_edge function in std_logic_1164,
>> that's incorrect. rising_edge( S ) is implemented as:
>>
>> s'event and to_x01( s ) = '1' and to_x01( s'last_value ) = '0'
>>
>> which means, s is changing (first clause), the current value of s is
>> either '1' or 'H' (second clause) and before the change, s was either '0'
>> or 'L' (final clause). So they are not the same.
>>
>> However, synthesis tools tend to treat them the same (those that
>> accept rising-edge--not all do). Hence, this is a potential source of
>> pre- and post-synthesis differences in behavior.
>>
>> Hope this helps,
>>
>> Paul
>>
>> --
>> Paul Menchini | me...@mench.com | "Every damn thing is your
>> Menchini & Associates | www.mench.com | own fault if you're any
>> P.O. Box 71767 | 919-479-1670[v] | good."
>> Durham, NC 27722-1767 | 919-479-1671[f] | -- Ernest Hemingway
Actually, after I posted that, I found out that they are
slightly different, although they do produce the same result for
synthesis. Sorry for my mistake!
It does seem, however, that the rising_edge() function in the
std_logic_1164 package might have to change because the Draft 1076.6
standard does not allow the 'LAST_VALUE attribute.
Wade D. Peterson
>rising_edge and falling_edge is not supported by Synopsys for synthesis.
>--
>Regards
>Hans Lindkvist
That's surprising. I've got a copy of the IEEE 1164-1993 (VHDL)
standard here, and it says rising_edge() and falling_edge() are part
of the standard. Does that mean that Synopsys doesn't follow the IEEE
standards?
Rick Collins
Wade D. Peterson wrote:
It seems that for synthesis, any given vendor is free to implement a subset
of the VHDL standard. I have been told that this is true for ALL vendors.
Each one implements a slightly different subset for synthesis, so that
although your design may be portable for simulation, it might not produce the
same (if any) hardware with different vendors.
Can anyone clarify this last statement? If a vendor implements a different
subset of synthesis, can it produce DIFFERENT hardware from another vendor?
Or must a vendor either produce the SAME hardware or simply fail to compile?
Rick Collins
Spikey
rh...@hal.ee.Virginia.EDU (Robert H. Klenke) wrote:
snip
> Actually, after I posted that, I found out that they are
>slightly different, although they do produce the same result for
>synthesis. Sorry for my mistake!
> It does seem, however, that the rising_edge() function in the
>std_logic_1164 package might have to change because the Draft 1076.6
>standard does not allow the 'LAST_VALUE attribute.
Any particular reason why the 'last_value is not allowed in the
draft 1076.6 standard?
Was the 1076.6 draft defined by what is currently supported
by particular synthesis tools?
Is the standard defined so that all the vendors can instantly
claim compatibility without having to progress their tools?
B
*remove antijunk from address to rely*
Hans Lindkvist
Wade D. Peterson wrote:
>
> >rising_edge and falling_edge is not supported by Synopsys for synthesis.
>
> >--
> >Regards
> >Hans Lindkvist
>
> That's surprising. I've got a copy of the IEEE 1164-1993 (VHDL)
> standard here, and it says rising_edge() and falling_edge() are part
> of the standard. Does that mean that Synopsys doesn't follow the IEEE
> standards?
First, Synopsys do not support VHDL-93 for synthesis only VHDL-87, and what i
know they will not support VHDL-93.
Second, I asked them a Synopsys Apps. Engineer about rising/falling_edge and the
answer I got was that they decided to do it like that, an answer, as you may
understand, annoyed me quite a lot. The theory I have is that Synopsys DC can't
handle EVENT statements whithin functions.
--
Regards
Hans Lindkvist
Sam Falaki
What's the big deal with using " IF clk'event AND clk = '1' " Anyways?
At least you know it synthesises on ALL the tools.
Sam Falaki
Phani Putrevu
Rick Collins wrote:
> Can anyone clarify this last statement? If a vendor implements a different
> subset of synthesis, can it produce DIFFERENT hardware from another vendor?
> Or must a vendor either produce the SAME hardware or simply fail to compile?
>
> Rick Collins
Check out
www.eda.org/swig
The synthesis ionteroperability Working group is developing a standard
semantics for VHDL RTL synthesis.
Phani
------------------------------------------------------------------------------
Phani K Putrevu |email : pput...@ececs.uc.edu
MS - Comp Engg |Phone : 513-281-1154 (home)
University of Cincinnati | 513-556-0904 (Off)
www.ececs.uc.edu/~pputrevu|Addr : 3018 Marshall Av. #2, Cincinnati OH
45220
------------------------------------------------------------------------------
zeids
Hans Lindkvist wrote:
> john_...@optilink.dsccc.com wrote:
> >
> > Hi, everyone, I'm wondering in VHDL, there seems to be 2 ways to implement
> > detection of rising clks:
> > 1. IF (clk'EVENT) AND (clk = '1') THEN
> > 2. IF rising_edge(clk) THEN
> >
> > What is the difference in them if my VHDL supports rising_edge()?
> > Are they actually the same? If not, which is better to use?
> >
> > thanks,
> > --john
> >
> > -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> > http://www.dejanews.com/ Now offering spam-free web-based newsreading
>
> rising_edge and falling_edge is not supported by Synopsys for synthesis.
>
> --
> Regards
> Hans Lindkvist
This is the most accurate answer I found. Rising_edge() is a function to be
called from the IEEE 1164 package. It is prefered over (clk'even and clk='1')
specially when used with std_logic data types.
The reason is when you have an std_logic{U,X,0,L,Z,W,L,H,-} signal, rising_edge()
only detect a transition from (0 to 1) rather than (X to 1) or (U to 1) or etc...
so consider that when you simulate
Zade Samuel
Sr. Design Engineer
Spectrum group
Cadence Design Systems INC.
Tom Palermo
zeids <ze...@cadence.com> wrote:
>
> This is the most accurate answer I found. Rising_edge() is a function to be
>called from the IEEE 1164 package. It is prefered over (clk'even and clk='1')
>specially when used with std_logic data types.
>The reason is when you have an std_logic{U,X,0,L,Z,W,L,H,-} signal, rising_edge()
>only detect a transition from (0 to 1) rather than (X to 1) or (U to 1) or etc...
>
>so consider that when you simulate
>
>Zade Samuel
>Sr. Design Engineer
>Spectrum group
>Cadence Design Systems INC.
>
Good point Zade! I guess by using (clk'event and clk='1') one may
detect anomalies in the clock signal. But that wouldn't be very
reliable of checking for all anomalies. The main reason I use the
functions rising_edge() and falling_edge(), are that they make for
more readable code.
Tom Palermo
Sr. Design Engineer
Cincinnati Electronics
Phil Ngai
In article <350BF4BB...@nospam.videotron.ca>,
Sam Falaki <fal...@nospam.videotron.ca> wrote:
>What's the big deal with using " IF clk'event AND clk = '1' " Anyways?
>At least you know it synthesises on ALL the tools.
If you have a series terminated clock and the clock value is 'H',
then it won't work, will it?
--
Have you switched to Microsoft Internet Explorer 4 yet?
Garry Allen
Tom Palermo wrote:
>
<previous comments deleted>
> Good point Zade! I guess by using (clk'event and clk='1') one may
> detect anomalies in the clock signal. But that wouldn't be very
> reliable of checking for all anomalies. The main reason I use the
> functions rising_edge() and falling_edge(), are that they make for
> more readable code.
>
> Tom Palermo
> Sr. Design Engineer
> Cincinnati Electronics
think they are also preferable because there is less chance for typing
errors in the code. But My designs are also required to support
different VHDL synthesis tools. One problem I have found is that
Synopsys in particular does not have the IEEE numeric libraries nor does
it support VHDL-93.
So-
(1) Is there some way of doing conditional compilation depending on the
synthesis tool/ So if I am using the FPGA Express tool, the synthesis
tool includes the appropriate Synopsys libraries but if I a using the
Cypress tool it includes the Cypress libraries or...
(2) Has anyone created a library entity declaring rising_edge and
falling_edge for Synopsys? How?
Garry Allen
DSP Engineer
Australian Broadcasting Corporation Technology Research and Development
Sam Falaki
If you're using rising_edge() for readability then why don't you define
your own rising_edge function based on " clk'event and clk = '1' " ?
Rgds,
Sam Falaki
Tom Palermo
Garry Allen <gar...@abc.gov.au> wrote:
>So-
>(1) Is there some way of doing conditional compilation depending on the
>synthesis tool/ So if I am using the FPGA Express tool, the synthesis
>tool includes the appropriate Synopsys libraries but if I a using the
>Cypress tool it includes the Cypress libraries or...
Garry, I agree with Sam, write your own function for rising_edge and
falling_edge functions. The functions are defined as events occuring
between '0' and '1'.
>2) Has anyone created a library entity declaring rising_edge and
>falling_edge for Synopsys? How?
Don't know about that, I use the packaged libraries.
We use Exemplar tools, and many of the libraries distributed with
their software were writen by other companies (including Synopsys).
They all have the typical disclaimers and "distributed without
restriction provided that this copyright statement is not removed".
Unfortunately, the standard 1164 library that defines the rising_edge
and falling_edge functions do not have any ownership attached so it is
probably covered by our software license agrrement. You might try
contacting Exemplar for a copy.
Sam Falaki
Phil Ngai wrote:
> In article <350BF4BB...@nospam.videotron.ca>,
> Sam Falaki <fal...@nospam.videotron.ca> wrote:
> >What's the big deal with using " IF clk'event AND clk = '1' " Anyways?
> >At least you know it synthesises on ALL the tools.
>
> If you have a series terminated clock and the clock value is 'H',
> then it won't work, will it?
>
Can you please elaborate with a synthesis example? I'm not sureI follow
you.
Thanks,
Sam
David Bishop
Phani Putrevu wrote:
> Check out
> www.eda.org/swig
> The synthesis ionteroperability Working group is developing a standard
> semantics for VHDL RTL synthesis.
I run this web page. There has been ALOT of discussion about this topicthere
too. Take a look in the e-mail archives kept there.
It turns out that the next release of Synopsys, 98.08, is supposed to support
"rising_edge" and "falling_edge", according to the Synopsys hotline anyway.
--
David Bishop
INTERNET: dbi...@kodak.com | The opinions voiced are mine
US MAIL: 1194 West Ave, Hilton NY 14468 | and not my company's.
PHYSICAL: 43:17:17N 77:47:37W 281' |
Robert H. Klenke
The source for the IEEE 1164 package can be found on the RASSP
web page: http://rassp.scra.org. Go to the VHDL models section and
select standards packages.
ems
>Can you please elaborate with a synthesis example? I'm not sure I follow
>you.
in std_ulogic 'H' is a weak 1, and '1' is a forcing 1. "IF clk'event
AND clk = '1' " picks up transitions that you probably don't want, ie.
'H'->'1'. your suggestion is fine for type BIT, which only has values
'0' and '1'.
if you're worried about this you should use something like
" clk'event and clk = '1' and clk'last_value = '0' ".
Phil Ngai wrote:
> Have you switched to Microsoft Internet Explorer 4 yet?
are you serious?! time for a reality check...
evan (e...@nospam.riverside-machines.com)
Jonas Nilsson
ems wrote:
> " clk'event and clk = '1' and clk'last_value = '0' ".
Which won't work if clk goes from 'L' to '1', or from '0' to 'H'...
Apply a strength reducer in the comparisons, i.e.:
clk'event and TO_X01Z(clk) = '1' and TO_X01Z(clk'last_value) = '0'
Regards,
Jonas
--
+---------------------------------------------------------------+
| Jonas Nilsson |
| HARDI Electronics AB Phone : +46-40-59 29 00 |
| Derbyvagen 6B Fax : +46-40-59 29 19 |
| SE-212 35 MALMO E-mail: jo...@hardi.se |
| SWEDEN WWW: http://www.hardi.se |
+---------------------------------------------------------------+
Robert H. Klenke
In article <35105590....@news.dial.pipex.com>, ems@see_signature.com (ems) writes:
|> On Wed, 18 Mar 1998 13:55:37 GMT, Sam Falaki
|> <fal...@nospam.videotron.ca> wrote:
|>
|> >Can you please elaborate with a synthesis example? I'm not sure I follow
|> >you.
|>
|> in std_ulogic 'H' is a weak 1, and '1' is a forcing 1. "IF clk'event
|> AND clk = '1' " picks up transitions that you probably don't want, ie.
|> 'H'->'1'. your suggestion is fine for type BIT, which only has values
|> '0' and '1'.
|>
|> if you're worried about this you should use something like
|>
But... according to the latest version of the 1076.6 Draft RTL
level synthesis standard, the 'LAST_VALUE attribute is not supported
for synthesis...
Rick Collins
Garry Allen wrote:
> Robert H. Klenke wrote:
> >
> <my question clipped>
> > |>
> <Tom's comments clipped>
> >
> > The source for the IEEE 1164 package can be found on the RASSP
> > web page: http://rassp.scra.org. Go to the VHDL models section and
> > select standards packages.
> >
> > Bob
> Thanks for everyone's replies. I attempted to write my own library
> functions for rising_edge and falling_edge in FPGA Express (The Synopsys
> ...snip...
> implementation of the libraries and...
>
> A language extension? that would be nice is something similiar to the
> #IFDEF that C has so we could conditionally choose to include the
> appropriate libraries.
> Garry Allen
I remember that in the old days of C programming, #define and #ifdef were
handled by a preprocessor. There was actually a separate program to perform
those functions. It would take in your source with #defines and spit out
source without them. Why couldn't you use this same program to process VHDL
containing the same #ifdef functions?
Rick Collins
Garry Allen
Robert H. Klenke wrote:
>
<my question clipped>
> |>
<Tom's comments clipped>
>
> The source for the IEEE 1164 package can be found on the RASSP
> web page: http://rassp.scra.org. Go to the VHDL models section and
> select standards packages.
>
> Bob
Thanks for everyone's replies. I attempted to write my own library
functions for rising_edge and falling_edge in FPGA Express (The Synopsys
of theose synthesis tools that currently only supports VHDL-87. I had to
port my code from Cypress Warp using some ieee library functions and
some of its own (particularly the numeric libraries used for
counters....) FPGA Express has internal Synopsys libraries for the same
functions. I have demoed some synthesis tools including Synplicity which
do use the ieee numeric libraries (and rising_edge and..) Unfortunately
our departmental budget will not stretch to these at the moment. So it
means that if I have to move from one manufacturer to another, it
appears that currently I have to modify the code to support their