unsigned to bit_vector

[chak]

hi every body,
could any body suggest me how to convert unsigned to bit vector......
and bitvector to unsigned with an exmaple.i will be very thank full
thanx in advance
chakri

[Egbert Molenkamp]

see:
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#vec_conversion

Egbert Molenkamp

"chak" <chak...@www.com> wrote in message
news:5dd17323.02041...@posting.google.com...

[feedback]

"chak" <chak...@www.com> a écrit dans le message de news:
5dd17323.02041...@posting.google.com...

> cThe std_logic_arith package in the ieee library includes three sets of
functions to convert values between SIGNED and UNSIGNED types and the
predefined type INTEGER.

CONV_INTEGER--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or
STD_ULOGIC to an INTEGER value. The size of operands in CONV_INTEGER
functions are limited to the range -2147483647 to 2147483647, i.e., to a
31-bit UNSIGNED value or a 32-bit SIGNED value.

CONV_UNSIGNED--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or
STD_ULOGIC to an UNSIGNED value with SIZE bits.

CONV_SIGNED--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or
STD_ULOGIC to a SIGNED value with SIZE bits.

CONV_STD_LOGIC_VECTOR--Converts a parameter of type INTEGER, UNSIGNED,
SIGNED, or STD_LOGIC to a STD_LOGIC_VECTOR value with SIZE bits. Example

Four versions of each function are available; the correct version for each
function call is determined through operator overloading.

Two operands are required for the CONV_UNSIGNED, CONV_SIGNED, and
CONV_STD_LOGIC_VECTOR functions: the value to be converted and an integer
that specifies the size of the converted value. If the value to be converted
is smaller than the expected size, the value is extended as necessary.

.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY adder IS
PORT (op1, op2 : IN UNSIGNED(7 DOWNTO 0);
result : OUT INTEGER);
END adder;

ARCHITECTURE maxpld OF adder IS
BEGIN
result <= CONV_INTEGER(op1 + op2);
END maxpld;

In this example, the ieee library is declared, and the std_logic_1164 and
std_logic_arith packages are specified. The inputs are declared with type
UNSIGNED, and the output is declared with type INTEGER.

maybe it could help you...
bye!

[Nicolas Matringe]

feedback wrote:
>
> "chak" <chak...@www.com> a écrit dans le message de news:
> 5dd17323.02041...@posting.google.com...
> > hi every body,
> > could any body suggest me how to convert unsigned to bit
> > vector...... and bitvector to unsigned with an exmaple.i will
> > be very thank full thanx in advance
> cThe std_logic_arith package in the ieee library includes three
> sets of functions to convert values between SIGNED and UNSIGNED
> types and the predefined type INTEGER.
>

[...]

> In this example, the ieee library is declared, and the
> std_logic_1164 and std_logic_arith packages are specified. The
> inputs are declared with type UNSIGNED, and the output is
> declared with type INTEGER.

You should use the standard "numeric_std" library instead of the std_arith* that
are NOT standard despite their names.
Converting signed or unsigned to std_logic_vector is just a type casting:
slv_value <= std_logic_vector(uns_value)
If you need to convert integers... you'll have to use the conversion functions
TO_SIGNED, TO_UNSIGNED or TO_INTEGER

--
Nicolas MATRINGE IPricot European Headquarters
Conception electronique 10-12 Avenue de Verdun
Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 02 http://www.IPricot.com/

[sweir]

chak, std_numeric provides direct conversions between unsigned and
std_logic_vector. Bit_vector bits only take on '1' and '0'. Are you sure
you want to use them?

use ieee.numeric_std.all ;
...
signal some_unsigned_value : unsigned( 7 downto 0 ) ;
signal some_std_logic_value : std_logic_vector(7 downto 0 ) ;
signal another_unsigned_value : unsigned( 7 downto 0 ) ;
...

some_unsigned_value <= to_stdlogicvector( some_unsigned_value ) ;
another_unsigned_value <= to_unsigned( some_std_logic_value ) ;
...

If you need to convert to bit vectors, you need to decide what how you want
X,Z,U etc to translate to '1's and '0's, since bit only takes on '1', or
'0'. If you are going to synthesize, you should really stay with
std_logic_vector, and its subsets, signed, and unsigned.

Regards,

"chak" <chak...@www.com> wrote in message
news:5dd17323.02041...@posting.google.com...

[Renaud Pacalet]

chak a écrit :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
...
signal BV: BIT_VECTOR(15 downto 0);
signal UV: UNSIGNED(1 to 16);
...
BV <= TO_BITVECTOR(STD_ULOGIC_VECTOR(UV));
UV <= UNSIGNED(TO_STDULOGICVECTOR(BV));

As suggested by Egbert the FAQ is a good starting point if you want
to understand all this.

Regards.
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pac...@enst.fr
###### Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ ######

[lesya.b...@noaa.gov]

Dear Renaud,

I also need to convert unsigned to bit vector...... and bit vector to unsigned. Unfortunately, I need to use
USE ieee.numeric_bit.all;

When I add
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

my program gives me an error (vcom-1078) Identifier "unsigned" is not directly visible.

Do you know any other way to unsigned to bit vector...... and bit vector to unsigned using USE ieee.numeric_bit.all;

Thanks!

Have a nice evening,
Lesya

[diog...@gmail.com]

With a context clause consisting of

library ieee;
use ieee.numeric_bit.all;

The conversion between the unsigned type declared in numeric_bit and bit_vector can be accomplished explicit type conversion between closely related types:

entity foo is
end entity;

architecture fum of foo is
signal unsigned_vector: unsigned (7 downto 0):= "11001010";
signal bit_val: bit_vector (7 downto 0);
begin
bit_val <= bit_vector(unsigned_vector);
end architecture;

unsigned is defined as an array natural range of type bit in package numeric_bit while bit_vector is defined as an array natural range of type bit in package standard. This makes the two types closely related, both arrays with the same element type, dimensionality and index type.

This context clause and associated entity/architecture pair analyzes, elaborates and simulates.

Conversion to unsigned is also accomplished by explicit type conversion:

architecture fie of foo is
signal unsigned_vector: unsigned (7 downto 0):= "11001010";
signal bit_val: bit_vector (7 downto 0);
signal un_signed: unsigned (7 downto 0);
begin
bit_val <= bit_vector(unsigned_vector);
un_signed <= unsigned(bit_val);
end architecture;

And this also analyzes, elaborates and simulates, differing from the previous architecture by doing conversion between unsigned and bit_vector and bit_vector and unsigned.

So as you can see from the rest of the answers you can see there is confusion on which declared unsigned to which you're referring.

In those cases where you need to express a VHDL design specification with both unsigned type declarations visible you could partition by visibility. For instance you could specify use clauses as process declarative items in a process statement's process declarative part. You'd communicate between the two processes via signals declared from types visible in both declarative regions.

For example one process statement can have a use clause

use ieee.numeric_std.all;

and use ieee.numeric_std.unsigned. While another process statement can have

use ieee.numeric_bit.all;

and use ieee.numeric_bit.unsigned.

You'd communicate between the two processes using signals whose types are visible to both declarations (e.g. bit_vector, std_logic_vector). Any unsigned types would be variables declared as process declarative items.

You could also use selected names:

library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fuu is
end entity;

architecture fee of fuu is
signal unsigned_vector: ieee.numeric_bit.unsigned (7 downto 0)
:= "11001010";
signal bit_val: bit_vector (7 downto 0);
signal un_signed: ieee.numeric_bit.unsigned (7 downto 0);
signal unsigned_slv: ieee.numeric_std.unsigned (7 downto 0);
signal bit_unsigned: ieee.numeric_bit.unsigned (7 downto 0);
begin
bit_val <= bit_vector(unsigned_vector);
un_signed <= ieee.numeric_bit.unsigned(bit_val);
unsigned_slv <= ieee.numeric_std.unsigned(to_stdlogicvector(bit_val));
bit_unsigned <= ieee.numeric_bit.unsigned(
to_bitvector(std_logic_vector(unsigned_slv))
);
end architecture;

Selected names overcome the issue of ambiguity with two types named unsigned.

(And this example also analyzes, elaborates and simulates)