division of two 4-bit vectors
My Name
I am sorry, i did not look for this topic on this forum, but i need
help, i am suposed to program a simple calculator in vhdl, and program
it on spartan 3 FPGA board... My assingment is to make a simple
calculator, i need to enter a two numbers (that are a 4 bit vectors) and
then enter a operand ( +, -, * or /). on my vhdl code everything is
working except division ( / ). and i dont know how to divide a two 4-bit
vectors..... please can anybody can help me... sorry for my bad
english.....:confused:
--
goranbm
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Rob Gaddi
I don't know of of any synthesis tool that supports division natively.
Generally you'll have to code the divide yourself as a serial divider;
one bit per clock tick. Google is your friend if you need some
steering on the algorithm.
That said, for 2 4-bit vectors you could also just implement division
as a table lookup ROM, but that solution doesn't scale well.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Jonathan Bromley
>
>I am sorry, i did not look for this topic on this forum, but i need
>help, i am suposed to program a simple calculator in vhdl, and program
>it on spartan 3 FPGA board... My assingment is to make a simple
>calculator, i need to enter a two numbers (that are a 4 bit vectors) and
>then enter a operand ( +, -, * or /). on my vhdl code everything is
>working except division ( / ). and i dont know how to divide a two 4-bit
>vectors..... please can anybody can help me... sorry for my bad
>english.....:confused:
For such tiny numbers, you could do "kindergarten division":
repeatedly subtract the divisor from the dividend, counting
how many times you do the subtraction, until the subtraction
would give a negative result. This could even be done
as a purely combinational function - it would create truly
horrible hardware, but it would work:
signal dividend, divisor, quotient, remainder:
unsigned(3 downto 0);
.....
process (dividend, divisor)
variable v: unsigned(3 downto 0);
variable done: boolean;
begin
v := dividend;
done := false;
for i in 0 to 15 loop
if not done then
if v < divisor then
quotient <= to_unsigned(i, 4);
remainder <= v;
done := true;
else
v := v - divisor;
end if;
end if;
end loop;
end process;
For extra credit, explain why I used a "done" flag
and a "for" loop, instead of a "while" loop.
Please, please promise you won't try to use that
for anything serious.....? And please promise that
you will say something in your assignment report
about division by zero?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan...@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
kennhe...@sympatico.ca
wrote:
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
And in a slighly more tongue-in-cheek answer which is however
completely serious, try using the VHDL "&" operator. It will give you
a result as an unreduced fraction. This might not be what you thought
you wanted but has the obvious advantage of retaining full arithmetic
precision and cleanly handling division by zero.
signal numerator, denominator : bit_vector(3 downto 0);
result :bit_vector(7 downto 0);
result <= numerator & denominator;
Seriously, without defining what your output needs to be, there's very
little point asking how to do it. The division operator over Zmod16 is
not closed over any simple field representable by uniformly spaced
values (which is probably what you might be asking for) unless you use
fractions mod LCM([1...15]). If you just want to implement a random
arithmetic hack that approximates 256 distinct values, use a ROM or
the code above.
- Kenn
Jonathan Bromley
wrote:
>The division operator over Zmod16 is
>not closed over any simple field representable by uniformly spaced
>values
That is an example of what my colleague Alan calls
"unfair use of long sentences" and is, I think,
what the diplomats might call "disproportionate
response".....
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan...@MYCOMPANY.com
My Name
can you provide a code for that kind of division, because i am new at
this kind of programing, so i dont know where to shearc ???? pliz, if it
is not a trouble, tnx :D
My Name
i have another problem, if you can help me..... it is just a college
project, it is not anything serious... my group an me, made a vhdl code
for calculator that uses a State machine, and it can do a math
operations and logical operations with two 4 bit vectors. Today we had a
meeting with teacher, and he just said that this calculator is for small
kids :) so hi said that we need to do a calculator, that will work with
biger numbers, 4 digit numbers ( max. 9999 ) it needs to have only math
and logical operations..... input comes from a keyboard..... so can you
help me please, i am from Croatia, im 21 years old, and my name is
Goran... This is my first project in vhdl language, so please help me, i
will be very grateful.... thanks in advance....
kennhe...@sympatico.ca
Hi Goran,
There are three things you need to figure out. The first thing is to
understand how to divide numbers. The second thing is to understand
how to do that division in hardware. The last thing is to code that
hardware in VHDL. (Apparently, the philosophical issues regarding the
mapping of mathematical ideas to std_logic_vectors are inflammatory!)
The simplest way to understand the first thing is to see that ordinary
"schoolboy-method" long division will work just as well if you write
the numbers in binary as if you write them in decimal. Once you can do
long division of two numbers in binary with pencil and paper you are
halfway there.
The simplest way to understand the second thing is to see how your
long division can be created with shift registers, subtractor, and
adders, and what order you need to do all the individual steps. Now
you are 90% of the way there.
The last step is just VHDL coding. If you know what you want to build
you can usually see how to make it happen in code. Once you have a
more specific problem, let us know.
The completely opposite approach is to look for some VHDL code on
google and just play with it until you get it to work. Personally, I
think you will learn more using the first approach.
- Kenn
Aiken
input to your Simulation program?
On Feb 12, 12:49 pm, My Name <myemail@a_domain.com> wrote:
My Name
i just need to input a 4 digit number from a keyboard to simulation....
if it is possible....
Dave
If you're just trying to get data into the simulation, and not have it
coded into the VHDL, maybe file I/O is what you want.
Dave
Benjamin Couillard
wrote:
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
You have used the for loop because the number of iterations must be a
constant.
The done flag is used to stop the calculations when we're done because
if we only need 3 iterations, we don't need to calculate anything in
the last 13 iterations.
Is that it?
Benjamin Couillard
wrote:
The number of iterations in a loop must be a constant for synthesis
IIRC.
Andy
>
> - Show quoted text -
Most synthesis tools require "static" (from a synthesis POV) loop
bounds, which may or may not be constants. For instance, because for-
loops are unrolled for synthesis, the loop index becomes static, which
means that the loop index can form the bounds of an inner loop.
You can use an exit statement, executed under a static or dynamic
condition, to modify the loop iteration boundaries too.
Andy