Unary reduction OR .... in VHDL

[LIJO]

HI all,
Any equivalent for verilog
| -- Unary reduction OR .... in VHDL
Thanks
Lijo

[Kai Harrekilde-Petersen]

"LIJO" <lijo_ec...@hotmail.com> writes:

> HI all,
> Any equivalent for verilog
> | -- Unary reduction OR .... in VHDL

There are no built-in operator that does that in VHDL. Fortunately,
it is very easy to write a function to do it for you. Something along
the lines of:

function OR_reduce(d: std_logic_vector) return std_logic is
constant all_zeros: std_logic_vector(d'range) := (others => '0');
begin
if d = all_zeros then
return '0';
else
return '1';
end if;
end OR_reduce;

(Caveat syntax errors - I didn't run it through a compiler)

Regards,

Kai
--
Kai Harrekilde-Petersen <k...@vitesse.com> Opinions are mine...

[Jim Lewis]

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ; --- required for unsigned

signal or_reduce : std_logic ;
signal A : std_logic_vector(7 downto 0) ;

Or_reduce <= '1' when unsigned(A) = 0 else '0' ; -- using pkg above.

if you use the std_logic_unsigned package, it simplifies to:
Or_Reduce <= '1' when A = 0 else '0' ;

Alternately similar to the previous post, you can use a constant:
signal A_ZERO : std_logic_vector := (A'Range => '0') ;

Or_Reduce <= '1' when A = A_ZERO else '0' ;

Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:J...@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
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[Jim Lewis]

Unary reduction operators are something that being
considered for the next revision of the language
and it is likely they will be adopted.

If this is important to you, you might want to
make sure you participate in VHDL-200X.
For details, see Steve Bailey's posts.

Cheers,
Jim