Using Variable Length Strings in VHDL

[Jason LaPenta]

Hello,

I would like a string Variable in my testbench to help me keep track of
what is going on in the waveform display. I would like to set it to
strings of arbitrary length. My simulator complains that the strings are
uncontrained. Is there a way to set either uncontrained strings, or
contrained srings without making every string the same length?

I.E.

main_test_p : PROCESS IS
VARIABLE task : string := "IDLE";
BEGIN

task := "test number 1";
...
task := "test 2";
...
task := "broken now";
...
task := "work!";

END PROCESS;

Thanks
Jason

[Mike Treseler]

Jason LaPenta wrote:
>
> I would like a string Variable in my testbench to help me keep track of
> what is going on in the waveform display. I would like to set it to
> strings of arbitrary length. My simulator complains that the strings are
> uncontrained. Is there a way to set either uncontrained strings, or
> contrained srings without making every string the same length?

A string type variable must be declared with a fixed length.
An access string type variable say my_str_ptr, can point to
a variable length string (my_str_ptr.all).

Here's a code snippet to get you started.

-- Mike Treseler

. . .

type frame_pointer is access unsigned;
type string_pointer is access string;
type test_frame is
record
id_ptr : string_pointer;
frame_ptr : frame_pointer;
need_fcs : boolean;
expect_fcs_ok : boolean;
end record test_frame;
constant how_many_frames : natural := 10;
type test_frames is array (1 to how_many_frames) of test_frame;
shared variable table : test_frames; -- No constants of access type allowed

. . .

procedure load_test_data is
-- purpose: load shared variable

procedure incr (variable arg : inout natural ) is
begin arg := arg + 1; end procedure incr;
variable i : natural := 1;

begin -- procedure load_test_data

table(i).id_ptr := new string'("simple_ok");
table(i).frame_ptr := new unsigned'(x"001122334455665544332211");
table(i).need_fcs := true;
table(i).expect_fcs_ok := true;
incr(i); ----------------------------------------------------------------
table(i).id_ptr := new string'("stuff_good");
table(i).frame_ptr := new unsigned'(x"0123456789abcdefff55");
table(i).need_fcs := true;
table(i).expect_fcs_ok := true;
incr(i); ----------------------------------------------------------------

. . .

report("["& integer'image(frame_int) &
"] : ["& table(frame_int).id_ptr.all &"]");

[VhdlCohen]

>> I would like a string Variable in my testbench to help me keep track of
>> what is going on in the waveform display. I would like to set it to
>> strings of arbitrary length. My simulator complains that the strings are
>> uncontrained. Is there a way to set either uncontrained strings, or
>> contrained srings without making every string the same length?
>
>A string type variable must be declared with a fixed length.
>An access string type variable say my_str_ptr, can point to
>a variable length string (my_str_ptr.all).
>
>Here's a code snippet to get you started.

Another solution that might be easier to handle is to use a variable of fixed
string length, and clip/extend with ' ' unused portions of the string.
Thus, if V is a string of 55 characters,

V := TO55Char("at " & image(now) & "sig =" & heximage(sig));
-- // image package at my site.

--------------------------------------------------
-- To "n" char, -- extention/clip of a string
--------------------------------------------------
function To55Char (StringIn : string) return String55_Typ is
variable V : String55_Typ := (others => ' ');
begin
if StringIn'length > String55_Typ'length then
return StringIn(1 to String55_Typ'length);
else
V(1 to StringIn'length) := StringIn;
return V;
end if;
end To55Char;
-------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------