Integer to Std_Logic_Vector
mwthw...@my-deja.com
Can anyone help,
How can I convert from Type Integer to Std_Logic_Vector ?
Thanks
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Davor Lukacic
<Std_Logic_Vector> <= CONV_STD_LOGIC_VECTOR(<interger_value>,n)
where n ist the number of bits your vector should have.....
cheers
davor
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Srinivasan Venkataramanan
There is no *standard* conversion function for this (as far as
I know), but every vendor provides a "std_logic_arith" package in
"their" IEEE library. This package normally contains the function that
you are looking for:
For example I use Cadence, and in their STD_LOGIC_ARITH package, I see
-- CONVERSION TO STD_LOGIC_VECTOR FROM INTEGER
function To_StdLogicVector (oper: INTEGER; length: NATURAL) return
STD_LOGIC_VECTOR;
You check with your library/package.
I would really suggest you NOT TO DO THE ABOVE as this is not portable
among tools. Better start using "numeric_std" package which is
"STANDARD"! In this case you must declare the "vector" to be either
"SIGNED" or "UNSIGNED" and use
"TO_INTEGER" conversion function.
Hope this helps.
Regards,
Srini
In article <86hqp1$h5t$1...@nnrp1.deja.com>, mwthw...@my-deja.com wrote:
> Can anyone help,
> How can I convert from Type Integer to Std_Logic_Vector ?
> Thanks
> Sent via Deja.com http://www.deja.com/
> Before you buy.
* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
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charle...@my-deja.com
Srinivasan Venkataramanan <venkataraman...@philips.com>
wrote:
conversion functions already exist. The following package uses a
conversion function adapted from the numeric_std package.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
------------------------------------------------------------------------
-------------
package Conversion is
constant ZVec: std_logic_vector( 0 to 1 ) := (others => '0');
function INTEGER_TOSLV (ARG, SIZE: NATURAL) return std_logic_vector;
end Conversion;
------------------------------------------------------------------------
---------------
package body Conversion is
function INTEGER_TOSLV (ARG, SIZE: NATURAL) return std_logic_vector is
variable RESULT: std_logic_vector( SIZE - 1 downto 0 );
variable I_VAL: NATURAL := ARG;
begin
if ( SIZE < 1 ) then return ZVec;
end if;
for I in 0 to RESULT'LEFT loop
if ( I_VAL mod 2 ) = 0 then
RESULT(I) := '0';
else RESULT( I ) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not( I_VAL =0 ) then
assert false
report "INTEGER_TOSLV: vector truncated"
severity WARNING;
end if;
return RESULT;
end INTEGER_TOSLV;
end Conversion;
Charles
me...@mench.com
<venkataraman...@philips.com> wrote in article
<21a2fc87...@usw-ex0107-041.remarq.com>:
> There is no *standard* conversion function for this (as far as I
> know), but every vendor provides a "std_logic_arith" package in >
> "their" IEEE library. This package normally contains the function
> that > you are looking for:
Use numeric_std. It is standard, and portable, and contains the
desired conversion function.
"Std_logic_arith" is non-standard and so can vary from vendor to
vendor....
Paul
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Cadence Design Systems | www.orcad.com | probably man's best friend, and
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raja
there are some pcakges in numeric or arith where there are
some functions to convert integer to std_logic _vector . he can use
for example
std_logic_vector < = CONV_STD_LOGIC_VECTOR( integer
range);
you can check this some vhdl book
hope this helps
kamal
Srinivasan Venkataramanan wrote:
> Hi,
> There is no *standard* conversion function for this (as far as
> I know), but every vendor provides a "std_logic_arith" package in
> "their" IEEE library. This package normally contains the function that
> you are looking for:
>
Srinivasan Venkataramanan
In article <86i8g2$3tc$1...@mench.mench.com>, me...@mench.com wrote:
> On Mon, 24 Jan 2000 09:08:42 -0800, Srinivasan Venkataramanan
> <venkataraman...@philips.com> wrote in article
> <21a2fc87...@usw-ex0107-041.remarq.com>:
> > know), but every vendor provides a "std_logic_arith" package in
> >
> > "their" IEEE library. This package normally contains the
> function
> > that > you are looking for:
> desired conversion function.
I completely agree with you. I would not use STD_LOGIC_ARITH. But I
thought numeric_std provides functions only to convert from UNSIGNED,
SIGNED to INTEGER (related to this context) and not directly from or to
STD_LOGIC_VECTOR. Of-course we could use an explicit type conversion
etc. That's why I wrote "there is no *standard* conversion function",
please correct me if I am wrong.
Andy Rushton
the std_logic_vector. The lack of a direct conversion is a good thing,
because it differentiates between a bus representing an unsigned number
and a similar bus representing a signed number. If I remember right, the
std_logic_arith function assumes a signed notation but you might not
realise this assumption in using it.
The solution is to use the fact that std_logic_vector is similar to both
signed and unsigned and so the built-in type-conversions between array
types can be used. Thus:
slv <= std_logic_vector(to_unsigned(i, slv'length));
In this case I've converted the integer i using an unsigned
representation, then converted it to the std_logic_vector type. I could
just as easily do a signed representaition:
slv <= std_logic_vector(to_signed(i, slv'length));
I would say that the original poster is probably doing something wrong
using std_logic_vectors anyway. Generally, all numeric values are best
represented as signed or unsigned where the sign convention is then
quite obvious and the possibility of error much less. This avoids all
these problems which create questions starting "how do I..." or "why
does...".
Andy