I use a top level testbench that instantiates a test harness and a generic testcase like this:
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architecture tb of testbench is
component harness is
end component harness;
component testcase is
end component testcase;
begin
th: component harness;
tc: component testcase;
end architecture tb;
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The testcase entity is defined in one file and each testcase containing the stimulus are defined in separate testcase architecture files. I use VHDL configurations in the testbench to select the appropriate testcase:
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-- Test Configuration 1 (TCFG1)
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configuration tcfg1 of testbench is
for tb
for th : harness
use entity work.harness
generic map (
G_LOG_FILENAME => "tcfg1_log",
G_WIDTH => 34
);
end for;
for tc : testcase
use entity work.testcase(tc1)
generic map (
G_WIDTH => 34
);
end for;
end for;
end configuration tcfg1;
Then, simulating a specific testcase is done by targeting the corresponding configuration:
$ vsim ${VOPTS} work.tcfg1