Re: How could I output a real signal to std_logic_vector?

[Alan Fitch]

Will wrote:
> Hi all,
>
> I'm really new to VHDL. I need to output a real signal. How could I
> convert it to std_logic_vector? Or, could I output a real number
> directly?

It depends whether you want to create hardware. Real numbers aren't
synthesisable.

For simulation, you can convert from real to std_logic_vector using

library ieee;
use ieee.numeric_std.all;

....

s <= Std_logic_vector(to_unsigned(INTEGER(r), s'LENGTH);

where s is a std_logic_vector and r is real. This assumes are represents
a real value greater or equal to zero, and that it fits into a certain
size of std_logic_vector.

> BTW, is there any way that I could monitor variables during test bench
> simulation like debugging in other language?
>

Yes, it's tool dependent. Most tools can display variables on the
waveform display, and also have the facility to set breakpoints and
single step. Make sure you include debugging symbols when you analyze
your code,

regards
Alan

--
Alan Fitch
Doulos
http://www.doulos.com