Convert enumerate type to std_logic_vector

[Sylvain]

Hi,

I have the following code :

type my_type is (A, B, C, ...);
(...)
signal my_signal : my_type;

I would like to know if it is possible to access to one bit of
my_signal after a conversion to std_logic_vector. Something like
CONV(my_type)[i].

I can do it for integer with the function CONV_STD_LOGIC_VECTOR from
ieee.std_logic_arith library but it seems not to work for enumrate
type.

Thank's advance.

Sylvain

[Lähteenmäki Jussi]

Sylvain <sbn...@netcourrier.com> wrote:
Not sure what you are trying to do, but I often use the following kind
of enumeration (not sure if that's a word :) ) for state machines for
one-hot coding. it's pretty easy to change into anything...

type bus_states is (IDLE, ERR, ADDR, DATA);
attribute ENUM_ENCODING : STRING;
attribute ENUM_ENCODING of bus_states : type is "0001 0010 0100 1000";

regards,
juza

: I have the following code :

: Thank's advance.

: Sylvain

--
Juza

[Renaud Pacalet]

Sylvain a écrit :

> Hi,
>
> I have the following code :
>
> type my_type is (A, B, C, ...);
> (...)
> signal my_signal : my_type;
>
> I would like to know if it is possible to access to one bit of
> my_signal after a conversion to std_logic_vector. Something like
> CONV(my_type)[i].

If you're using enumerated types there can be two reasons:
1) You don't care about the binary representation of the different
values and decided to leave it to the synthesizer; not your case
because you care.
2) You prefer the meaningful labels to the ugly "0010"; must be your
case. Then, if you need to know the binary coding and want to
access some bits of it, I'll suggest using STD_ULOGIC_VECTOR
constants instead of enumerated types:
subtype MY_TYPE is STD_ULOGIC_VECTOR(3 downto 0);
constant A: MY_TYPE := "0010";
constant B: MY_TYPE := "0110";
constant C: MY_TYPE := "1010";
Having a signal S or variable V of type MY_TYPE you'll access one
bit of them with S(I) or V(I). No conversion is needed.

>
> I can do it for integer with the function CONV_STD_LOGIC_VECTOR
> from ieee.std_logic_arith library but it seems not to work for
> enumrate type.

Another suggestion: stop using Synopsys STD_LOGIC_ARITH package.
It's not standard, has nothing to do in IEEE library, seriously
compromises the portability of your code and will sooner or later be
totally obsolete. Use IEEE.NUMERIC_STD or IEEE.NUMERIC_BIT. The
conversion function from INTEGER to UNSIGNED (a type that has the
same definition as STD_LOGIC_VECTOR, just a different name) is
TO_UNSIGNED. And now, if you really want to perform the conversion
from your enumerated type to STD_LOGIC_VECTOR you can use this:

library IEEE;

type MY_TYPE is (A, B, C, D, E); -- Let's say 5 values.
signal MY_SIGNAL: MY_TYPE;
signal SINGLE_BIT: STD_LOGIC;
...
SINGLE_BIT <= TO_UNSIGNED(MY_TYPE'POS(MY_SIGNAL), 3)(1);
-- Convert MY_SIGNAL to INTEGER first with POS attribute applied to
-- MY_TYPE (leftmost value is numbered 0), convert this INTEGER to a
-- 3 bits UNSIGNED with the conversion function TO_UNSIGNED from
-- IEEE.NUMERIC_STD and then access bit #1.

But there is no guaranty that your synthesizer will use the same
simple coding... so it's a potential mismatch source.

Last advice if I may: do not use resolved types (such as STD_LOGIC)
if you don't intend to implement multiple drives logic. Always
prefer unresolved types (such as STD_ULOGIC).

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pac...@enst.fr

[Mike Treseler]

Sylvain wrote:

> I have the following code :
>
> type my_type is (A, B, C, ...);
> (...)
> signal my_signal : my_type;
>
> I would like to know if it is possible to access to one bit of
> my_signal after a conversion to std_logic_vector. Something like
> CONV(my_type)[i].

I think that Mr. Pacalet gave you the best answer

if you intend to identify vectors by name.

Here is another possibility if you intend
to identify bits.

You could use my_type as an
array *range* rather than as a signal.
In the sim example below, my_signal
of type vector_t has a range from
left to right of my_type.

You can pick out a bit by name:
my_signal(A), my_signal(B) etc.

-- Mike Treseler
----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity enum_range is
port (out_D : out std_logic );
end enum_range;

architecture sim of enum_range is

type my_type is (A, B, C, D, E, F);
type vector_t is array (my_type'left to my_type'right) of std_logic;
signal my_signal : vector_t;

what : process is
begin
my_signal <= "01WLHZ";
wait for 10 ns;
out_D <= my_signal(D);
wait for 10 ns;

assert my_signal(A) = '0' report "assertion error in enum_range";
assert my_signal(D) = 'L' report "assertion error in enum_range";
report "assertions complete";
wait;
end process what;

end sim;

[Tom Verbeure]

> If you're using enumerated types there can be two reasons:
> 1) You don't care about the binary representation of the different
> values and decided to leave it to the synthesizer; not your case
> because you care.
> 2) You prefer the meaningful labels to the ugly "0010"; must be your
> case. Then, if you need to know the binary coding and want to
> access some bits of it, I'll suggest using STD_ULOGIC_VECTOR
> constants instead of enumerated types:
> subtype MY_TYPE is STD_ULOGIC_VECTOR(3 downto 0);
> constant A: MY_TYPE := "0010";
> constant B: MY_TYPE := "0110";
> constant C: MY_TYPE := "1010";
> Having a signal S or variable V of type MY_TYPE you'll access one
> bit of them with S(I) or V(I). No conversion is needed.

What I dislike about the second method is that waveform viewerd isplay
enumerated types in text form, while displaying vectors as, well, vectors.
:-) Which makes it harder to understand what's going on in a statemachine.

A third solution is to keep on using enumerated types and make a function
that converts the enumerated type into an std_ulogic_vector. This is very
easy with the 'pos attribute (or function?).
Unfortunately, 'pos is not synthesizable by Synopsys (don't know about
other tools), but you can add an one-to-one mapping pragma to that function
so that Synopsys interprets it as a straight one-to-one mapping.

I agree that this seems a bit far fetched, but we have used it that way and
it worked fine, assumimg that you are happy with the standard enum mapping
of Synopsys.

Tom

[Clyde R. Shappee]

As this poster states, this will work to provide you with the std_logic_vector representation that you desire.  I did it slightly differently using a subtype as was shown in the Ashendon text.

   subtype CPLD_bus_states is std_logic_vector (8 downto 0);
   constant idle: CPLD_bus_states:=             "000000001";
   constant csds0:CPLD_bus_states:=             "000000010";
   constant csds: CPLD_bus_states:=             "000000100";
   constant wait_for_dtack:CPLD_bus_states:=    "000001000";
   constant transfer_ack:CPLD_bus_states:=      "000010000";
   constant wait_state:CPLD_bus_states:=        "000100000";
   constant CPLD_transfer_ack:CPLD_bus_states:= "001000000";
   constant dead_cycle:CPLD_bus_states:=        "010000000";
   constant turn_around:CPLD_bus_states:=       "100000000";

   signal CPLD_bus_state : CPLD_bus_states;

I used another type declaration and a process to provide a readout of the actual state with my names so I could see it in the simulaton.   The process that did the signal assignments for the simulation did not make any logic and the synthesizer did not complain.

Hope this helps.

Clyde

[Colin Marquardt]

Tom Verbeure <tom.ve...@verizon.no.sp.am.net> writes:

>> If you're using enumerated types there can be two reasons:

[...]

>> 2) You prefer the meaningful labels to the ugly "0010"; must be your
>> case. Then, if you need to know the binary coding and want to
>> access some bits of it, I'll suggest using STD_ULOGIC_VECTOR
>> constants instead of enumerated types:
>> subtype MY_TYPE is STD_ULOGIC_VECTOR(3 downto 0);
>> constant A: MY_TYPE := "0010";
>> constant B: MY_TYPE := "0110";
>> constant C: MY_TYPE := "1010";
>> Having a signal S or variable V of type MY_TYPE you'll access one
>> bit of them with S(I) or V(I). No conversion is needed.
>
> What I dislike about the second method is that waveform viewerd isplay
> enumerated types in text form, while displaying vectors as, well, vectors.
> :-) Which makes it harder to understand what's going on in a statemachine.

If the waveform viewer supports mnemonic maps, then it's just a little
inconvenience at the start of a simulation to set this up. Sometimes you
can even set up color coding in addition which also helps to quickly
identify "bad" cases.

Cheers,
Colin