Random Number Generator in VHDL
Lynn West
itegers and bit_vector or std_logic_vector type) in VHDL. I seem to
vaguely remember such but cannot find it in my books. (I have not yet
figured out how to master access to the FAQ for this newsgroup, so
cannot look there).
Obvously something could be conjured up with a set of differently-timed
clocks, but I am hoping for something simpler than that.
Thanks,
Lynn West
Mark Gonzales
Lynn West <lynn...@netcom.com> wrote:
>Is there a simple way to generate random numbers (preferably both
>itegers and bit_vector or std_logic_vector type) in VHDL.
Try this: (disclaimer: use at your own risk):
===========================
procedure RANDOM (variable Seed: inout integer; variable X: out real) is
----------------------------------------------------------------------
-- Random Number generator from:
-- The Art of Computer Systems Performance Analysis, R.Jain 1991 (p443)
-- x(n) := 7^5x(n-1) mod (2^31 - 1)
-- This has period 2^31 - 2, and it works with odd or even seeds
-- This code does not overflow for 32 bit integers.
----------------------------------------------------------------------
constant a : integer := 16807; -- multiplier 7**5
constant m : integer := 2147483647;-- modulus 2**31 - 1
constant q : integer := 127773; -- m DIV a
constant r : integer := 2836; -- m MOD a
constant m_real : real := real(M);
variable seed_div_q : integer;
variable seed_mod_q : integer;
variable new_seed : integer;
begin
seed_div_q := seed / q; -- truncating integer division
seed_mod_q := seed MOD q; -- modulus
new_seed := a * seed_mod_q - r * seed_div_q;
if (new_seed 0) then
seed := new_seed;
else
seed := new_seed + m;
end if;
X := real(seed) / m_real;
end RANDOM;
===========================
Mark
--
not speaking for Intel.
VhdlCohen
West) writes:
>Is there a simple way to generate random numbers (preferably both
>itegers and bit_vector or std_logic_vector type) in VHDL. I seem to
>vaguely remember such but cannot find it in my books.
Below is a number of sites that may have what you want. I found a random
package (but I can't remenber the site). Thus, I am putting a copy
(randm_pb.vhd)
it in my ftp site (see my signature).
For Std_Logic_Vector PN numbers, I use an LFSR technique.
This model is in my book, but for your convenience I am posting here.
I am also posting a simple PN number generator for integer type.
--------------------------------------------------------------------------
-----
--
-- Project : ATEP
-- File name : prg32_ea.vhd
-- Title : Process Demo
-- Description : Demonstrate automatic reiteration of a process
-- : by using a 32 bit pseudorandom number generator
-- : with a hardware implementation.
--
--------------------------------------------------------------------------
-----
-- Revisions :
-- Date Author Revision Comments
-- Sun Oct 23 08:01:37 1994 cohen Rev A Creation
--------------------------------------------------------------------------
-----
library IEEE;
use IEEE.Std_Logic_1164.all;
entity PRG32_Nty is
generic (Seed_g : Std_Logic_Vector(31 downto 0)
:= "10000000000011111000000000000110");
port (PRG32 : out Std_logic_vector(31 downto 0));
end PRG32_Nty;
architecture PRG32_a of PRG32_Nty is
signal Seed_s : Std_Logic_Vector(31 downto 0) :=
Seed_g;
begin -- PRG32_a
--------------------------------------------------------------------------
---
-- Process: PRG32_Lbl
-- Purpose: Demonstrate generation of a pseudorandom number generator
-- with the seed stored in a signal.
--------------------------------------------------------------------------
---
PRG32_Lbl : process
variable Xgate_v : STD_LOGIC; -- Output of xor gate begin
begin -- process PRG32_Lbl
Xgate_v := Seed_s (31) xor Seed_s (30) xor
Seed_s (10) xor Seed_s (0);
Seed_s <= not Xgate_v & Seed_s (31 downto 1);
wait for 100 ns;
end process PRG32_Lbl;
--------------------------------------------------------------------------
---
-- Process: SendPrg_Lbl
-- Purpose: Transfers Prf number to output
--------------------------------------------------------------------------
---
SendPrg_Lbl : process (Seed_s)
begin -- process SendPrg_Lbl
PRG32 <= Seed_s;
end process SendPrg_Lbl;
end PRG32_a;
-------------------------
--------------------------------------------------------------------------
-----
--
-- Project : ATEP
-- File name : randm_ea.vhd
-- Title : Pseudo Random number generator
-- Description : Integer PN generator
--
--------------------------------------------------------------------------
-----
-- Revisions :
-- Date Author Revision Comments
-- Tue Dec 27 16:27:54 1994 cohen Rev A Creation
--------------------------------------------------------------------------
-----
entity Random_Nty is
end Random_Nty;
architecture Random_a of Random_Nty is
signal Random_s : integer;
begin -- Random_a
--
PseudoRandom_Lbl: process
variable Seed_v : INTEGER := 17654;
constant Multiplier_c : INTEGER := 25173;
constant Increment_c : INTEGER := 13849;
constant Modulus_c : INTEGER := 65536; -- rollover value
begin
SEED_v := (Multiplier_c * Seed_v + INCREMENT_c) mod Modulus_c;
Random_s <= Seed_v;
wait for 10 ns; --repeat process every 10 ns
end process PseudoRandom_lbl;
end Random_a;
Steve Hoeft
wrote:
> Steve Pope wrote:
> >
> > Hi Everyone,
> >
> > Are there any readily available, public-domain VHDL
> > simulators? I do not need anything fancy, or any
> > libraries, and a VHDL subset would probably work fine.
> > I would need to have a text interface (as opposed to
> > a GUI). I am on a SUN running 4.1.3.
> >
> > Thanks for any help.
> >
> > Steve
>
If you can use a PC, try http://together.net/~thibault/
for green mountain's VHDL simulator. The share ware version is good enough
to get started and for about $100 or so the real version should be even
better.
+------------------------------------------------------------------------+
Steve Hoeft e-mail s...@wdl.loral.com This is my very
personal opinion!
Loral WDL voice (408)473-6479
3200 Zanker Rd. fax (408)473-4093
San Jose, CA 95134
Lun Ye
Kalpesh Patel <kalp...@symbol.com> wrote:
>Steve Pope wrote:
>>
>> Hi Everyone,
>>
>> Are there any readily available, public-domain VHDL
>> simulators? I do not need anything fancy, or any
>> libraries, and a VHDL subset would probably work fine.
>> I would need to have a text interface (as opposed to
>> a GUI). I am on a SUN running 4.1.3.
>>
>> Thanks for any help.
>>
>> Steve
>
>
>Model Technology for PC running windows. Sorry no public domain
>simulators!
>
>--
>
> .
> _| _/ _|_|_|_| \_|_/
> _| _/ _| _| ______________.ooO__(_o
>o_)___Ooo.______________
> _| _/ _| _| (_)
> _| _/ _| _|
> _| _/_\ _|_|_|_| Kalpesh Patel | Symbol Technology
> _|_/ _\ _| (516) 563-2400 @3292 | 116 Wilbur Place, B3
> _| _\ _| kalp...@symbol.com | Bohemia, NY 11716
> _| _\ _|
> _| _\ _| .ooO Ooo.
>______________________________________\ (_________)
>/__________________
> \_) (_/
hmmmm...how about the $99 one? they raised the price?
Lun
--
USE std.disclaimers.ALL; --Lun Ye (513) 556-4772
ASSERT flame REPORT "who cares?" SEVERITY note; --ECE and CS Dept, ML #30
--URL: http://www.ece.uc.edu/~lunye/homepage.html --U. of Cincinnati, OH 45221
Steve Pope
>Steve Pope wrote:
>> Are there any readily available, public-domain VHDL
>> simulators? I do not need anything fancy, or any
>> libraries, and a VHDL subset would probably work fine.
>> I would need to have a text interface (as opposed to
>> a GUI). I am on a SUN running 4.1.3.
>
>Model Technology for PC running windows. Sorry no public domain
>simulators!
>
product information and am awaiting a response.
There is one simulator in the public domain (thanks to everyone
who emailed me regarding it) in the "alliance" distribution.
It is called asimut. I am presently attempting to compile this one.
Anyone who has had any luck installing this thing, and is
bored enough to answer a few questions, feel free to contact me. :)
Thanks again.
Steve
Steve Pope
> If you can use a PC, try http://together.net/~thibault/
> for green mountain's VHDL simulator. The share ware version is
> good enough to get started and for about $100 or so the real
> version should be even better.
Thanks. Is there an ftp-able version of this? (I'm web-browser
challenged at the moment). Or, a point of contact for Green
Mountain.
Steve
Thomas Lindblad
But the Alliance and its parts only runs on SUN and other UNIX machines,
right? It would be great to have Alliance under OS/2!
Ciao // Thomas
bk...@hotmail.com
> Is there a simple way to generate random numbers (preferably both
> itegers and bit_vector or std_logic_vector type) in VHDL. I seem to
> figured out how to master access to the FAQ for this newsgroup, so
> cannot look there).
>
> Obvously something could be conjured up with a set of differently-timed
> clocks, but I am hoping for something simpler than that.
>
> Thanks,
>
> Lynn West
...
library my_lib;
use my_lib.my_package.all;
...
signal rand_packet_delay : std_logic_vector(3 downto 0) := "1000";
signal rand_packet_delayi: integer;
...
rand_packet_delay <= f_my_rand f_my_rand (4, rand_packet_delay);
--write(my_line, rand_packet_delay'path_name);
--write(my_line, string'(" "));
--hwrite(my_line, rand_packet_delay);
--write(my_line, string'(" "));
--write(my_line, now);
--writeline(output, my_line);
--packet send ended
if(unsigned(rand_packet_delay) > 3) then
rand_packet_delayi <= conv_integer(rand_packet_delay);
else
rand_packet_delayi <= conv_integer(rand_packet_delay) + 3;
end if;
for j in 1 to rand_packet_delayi loop
wait until rx_clk'event and rx_clk = '1';
end loop;
Recently I have improved the random generation using c code and VHPI. First some links , which show simple examples of c code interface for GHDL.
Please read also
http://bknpk.ddns.net/my_web/SDIO/ip_ttl_filter_d_b_packets_rand.html