Thanks,
Hamish
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Hamish Moffatt, StudIEAust ham...@debian.org, ham...@moffatt.nu
Student, computer science & computer systems engineering. 4th year, RMIT.
http://hamish.home.ml.org/ (PGP key here) CPOM: [****** ] 64%
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Kind regards,
Jan
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===================================================================
Jan Zegers === Easics ===
General Manager === VHDL-based ASIC design services ===
Tel: +32-16-395 601 ===================================
Fax: +32-16-395 619 Interleuvenlaan 86, B-3001 Leuven, BELGIUM
mailto:ja...@easics.be http://www.easics.com
> Does anyone have some VHDL, or a description of the algorithm (NON-table
> based) for a 16 bit CRC? There's been plenty of 32-bit versions posted
> here (I saw them on Dejanews) but I am looking for a 16-bit one.
There are different versions of 16 bit CRC (they have different
generating polynomials). Most algorithms are specified on a serial
form, but you can easily convert it into parallel form using any
number of bits as input. Here's the CCITT CRC-16 serial version with
the generating polynomial X^16+X^12+X^5+1:
c15 = c0 XOR d
c14 = c15
c13 = c14
c12 = c13
c11 = c12
c10 = c11 XOR c0 XOR d
c9 = c10
c8 = c9
c7 = c8
c6 = c7
c5 = c6
c4 = c5
c3 = c4 XOR c0 XOR d
c2 = c3
c1 = c2
c0 = c1
c0 is the MSB, d is the input.
Petter
Not responsible for mistakes in any of the above information.
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________________________________________________________________________
Petter Gustad 8'h2B | (~8'h2B) - Hamlet http://home.sol.no/~pegu
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("pegu\100computer\056org\nmy opinions only\n");}