SUMMARY: Do people use ieee.std_logic_1164?

[Daniel R. Kegel]

I asked:
>From: da...@blacks.jpl.nasa.gov (Daniel R. Kegel)
>Newsgroups: comp.lang.vhdl
>Subject: Do people use ieee.std_logic_1164 for tristate signals?
>Date: 23 Feb 93 17:32:52 GMT
>
>Hi,
>I'm trying to figure out whether I should yell at all my synthesis vendors to
>support IEEE 1164 style tristate signals. Right now, Exemplar does
>support it, but Cypress uses their own type (x10z) for tristate signals.
>This is going to cause me trouble when I try to simulate models
>written for the two different synthesis packages together.
>
>Do the big synthesis vendors support 1164, or do they prefer some other
>logic type?
>-- Dan Kegel (da...@blacks.jpl.nasa.gov)

Reply #1:
>From: ko...@mksol.dseg.ti.com (David J Kopca)
>
>Yell real loud!
>
>You the user should not have to put up with different packages.
>Remember - you are the customer - you are supplying the $$$.
>
>With more users going to the 1164 package, VHDL will become
>more portable and easier to read (everyone will know the logic
>values).
>
>I suspect most of the ASIC libraries will be written just for the
>1164 package and nothing else. This may not directly help you,
>but it would be nice if we could have all of our parts work
>together without writing extra interfaces and packages.
>
>
>Good luck,
>
>Dave

Reply #2:
>From: cha...@sundiver.esd.sgi.com (Chris Hawley)
>
>Howdy, Dan:
> Yes, it's usually an enormous pain in the posterior, but no worse than
>solving the problems created whenever **any** new type is defined and is to
>be used in conjunction with any other type(s). Thanks to the miracle of
>strong type checking (BLEAH!), a natural barrier prevents inadvertent --
>or deliberate -- mixing of types, except by someone sufficiently determined
>who defines the necessary conversion functions required for such mixing.
>
> The good news is, once you've got a decent set of conversions in your
>grab bag, it's not dauntingly difficult to bend one conversion to another
>purpose/type; most of the work can be done with g/pat/s/...// .
>
>+ Do the big synthesis vendors support 1164, or do they prefer some other
>+ logic type?
>
> Some do, some don't. I imagine 1164 will become de rigeur, but from
>the little I've seen so far, it ain't there yet. One factor which impedes
>standardization is that, for the chip vendors to adopt 1164, they have to
>convince the folks who do chip testers to make the transition as well, or
>else bear the burden of translation themselves. A lot of the chip test
>languages (plus s/w, h/w) are barely up to the concept of bidirectional
>signals; most handle such by defining an 'expected output' and a mask value
>as one channel, plus a 'driven input' and another mask on a separate channel,
>then associating both channels (one put, one output) with the same physical
>device pin!!!
>
>
>--
> Christopher J. Hawley / esper / cha...@sundiver.esd.sgi.com
> Silicon Graphics, Inc. 01L-945 PSD phone: 415 / 390-1621 work
> Mountain View, CA 94039-7311 USA / 415 / 965-0754 home
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> .... somewhere in the spectrum between Real Love and a free lunch.
>

Reply #3:
>From: avls...@sn370.utica.ge.com (David W. Bishop)
>
>Dan:
>
>> I'm trying to figure out whether I should yell at all my synthesis vendors to
>> support IEEE 1164 style tristate signals.
>
>Yes, yell, add your voice to the fray.
>
>> Right now, Exemplar does
>> support it, but Cypress uses their own type (x10z) for tristate signals.
>
>Exemplar does it, but they don't do it right. If the part you are using
>does not support tristates directly then their tool errors out. You have
>to use it in "Chip" mode and turn their tristate flag on to make it work,
>and only on output ports. If you have more than one process driving a
>tristate bus then their tool complains. Don't know about Cypress.
>
>> This is going to cause me trouble when I try to simulate models
>> written for the two different synthesis packages together.
>
>Unfortunately yes. Have you tried to simulate with Exemplar's "int2evec"
>code yet? It doesn't work.
>
>> Do the big synthesis vendors support 1164, or do they prefer some other
>> logic type?
>
>Synopsys, The big one, does support 1164 "std_logic" as a tristage, although
>the internal tools have it aliased as "unsigned". I use vantage for all
>my VHDL simulation, and it likes it just fine.
>
> David Bishop
>
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