Default value on signal parameter of a procedure
Paul Uiterlinden
Are default values on signal parameters of a procedure allowed?
IKOS/Voyager does allow it, MTI produces the following warning: "Default
values are not allowed on signal parameters.".
When I look in the LRM, I cannot find why it should not be allowed.
Paragraph 2.1.1 describes the formal parameter list, and paragraph 4.3.3
describes the interface_signal_declaration, which clearly ends in "...:=
[static_expression]".
The declaration of my procedure is as follows:
PROCEDURE AMIClockRec
(
SIGNAL PosIn : IN Std_Logic;
SIGNAL NegIn : IN Std_Logic;
SIGNAL HalfClockPeriod : IN Time := 243 ns; -- Legal?
SIGNAL StopClock : IN Std_Logic := '0'; -- Legal?
SIGNAL ClockOut : OUT Std_Logic;
SIGNAL TmpClk : INOUT Std_Logic
);
This procedure should be instantiated by a concurrent procedure call.
The reason I have these default values is to be able to leave the two
signals unconnected (like in a component instantiation).
Any hints?
--
Paul Uiterlinden
Lucent Technologies
Bell Labs Innovations
Botterstraat 45 Tel : +31 35 687 4892
P.O. Box 18 Fax : +31 35 687 5964
1270 AA Huizen Email : uiter...@lucent.com
the Netherlands
Martin Radetzki
Paul Uiterlinden wrote:
>
> Are default values on signal parameters of a procedure allowed?
> IKOS/Voyager does allow it, MTI produces the following warning: "Default
> values are not allowed on signal parameters.".
>
> When I look in the LRM, I cannot find why it should not be allowed.
> Paragraph 2.1.1 describes the formal parameter list, and paragraph 4.3.3
> describes the interface_signal_declaration, which clearly ends in "...:=
> [static_expression]".
>
> The declaration of my procedure is as follows:
>
> PROCEDURE AMIClockRec
> (
> SIGNAL PosIn : IN Std_Logic;
> SIGNAL NegIn : IN Std_Logic;
> SIGNAL HalfClockPeriod : IN Time := 243 ns; -- Legal?
> SIGNAL StopClock : IN Std_Logic := '0'; -- Legal?
> SIGNAL ClockOut : OUT Std_Logic;
> SIGNAL TmpClk : INOUT Std_Logic
> );
>
> This procedure should be instantiated by a concurrent procedure call.
> The reason I have these default values is to be able to leave the two
> signals unconnected (like in a component instantiation).
>
> Any hints?
>
The (VHDL-1993) LRM forbids default expressions of formal signal
parameters in section 4.3.2 "Interface declarations" (page 59,
line 351). The reason is, I think, that a signal declaration
in a formal parameter list does not create a signal which could
be initialized. Rather, such formal signal parameter is only a
reference to a signal instantiated somewhere else.
Regards,
Martin
________________________________________________________________________
Martin Radetzki Tel.: **49-441-798-2988
OFFIS Research Institute Fax.: **49-441-798-2145
Escherweg 2 http://eis.informatik.uni-oldenburg.de/~martin
26121 Oldenburg, Germany e-mail: rade...@offis.uni-oldenburg.de
Martin Radetzki
I wrote:
>
> The (VHDL-1993) LRM forbids default expressions of formal signal
> parameters in section 4.3.2 "Interface declarations" (page 59,
> line 351). The reason is, I think, that a signal declaration
352, to be exact...
Paul Uiterlinden
Martin Radetzki wrote:
> The (VHDL-1993) LRM forbids default expressions of formal signal
> parameters in section 4.3.2 "Interface declarations" (page 59,
> line 351).
I still use VHDL-1987, and the LRM-1987 does not forbid it. It only forbids
default expressions in combination with mode LINKAGE and FILE types (page
4-9, fourth paragraph). So I still don't know whether it's allowed or not.
> The reason is, I think, that a signal declaration
> in a formal parameter list does not create a signal which could
> be initialized. Rather, such formal signal parameter is only a
> reference to a signal instantiated somewhere else.
Unless you leave the signal association OPEN, which is only allowed when
there is a default value.
Martin Radetzki
Paul Uiterlinden wrote:
>
> Martin Radetzki wrote:
>
> > The (VHDL-1993) LRM forbids default expressions of formal signal
> > parameters in section 4.3.2 "Interface declarations" (page 59,
> > line 351).
>
> I still use VHDL-1987, and the LRM-1987 does not forbid it. It only forbids
> default expressions in combination with mode LINKAGE and FILE types (page
> 4-9, fourth paragraph). So I still don't know whether it's allowed or not.
>
compiler, LEDA LVS, which can be switched between '87 and '93. Indeed,
it accepts the default expression in '87 mode and rejects it in '93
mode.
To my knowledge, MTI is capable of '93. Maybe that it does not relax
its checks on interface lists when you switch it to '87.
So, from a formal point of view, if the default expressions are not
forbidden in the LRM-1987, they are legal in VHDL-87. But I think this
was changed in VHDL-1993 for good reason, see below.
> > The reason is, I think, that a signal declaration
> > in a formal parameter list does not create a signal which could
> > be initialized. Rather, such formal signal parameter is only a
> > reference to a signal instantiated somewhere else.
>
> Unless you leave the signal association OPEN, which is only allowed when
> there is a default value.
>
To point out my view more detailed:
* All signals of a VHDL description are created statically during
static elaboration.
* A procedure call is dynamic. Assume a formal signal parameter was
open, i.e. not linked to one of the static signals. With or without
initialization, the simulator would have to create that signal
dynamically. This would contradict the static-signal-principle.