Selecting generic at simulation time.

[Niv (KP)]

I have a testbench which reads data from a memory, which is
initialised with data from a file, the file name is a generic in the
memory model.

Is there some way to start the simulation which then asks which file
I'd like to use to initialise the memory before the sim progresses?
TIA, Niv.

[Jonathan Bromley]

Most simulators have a command-line option to set generics
(or Verilog parameters) at elaboration time. For example, in
Mentor Modelsim/Questa, if your top-level has a string generic
called FILENAME:

vsim -gFILENAME=somefile.txt my_top_level_entity

See also the -G option which does similar things. Beware of
spaces and backslashes in filenames :-(

However, perhaps you want to read in the filename dynamically?
You can read from the INPUT file (keyboard) procedurally:

use std.textio.all; -- as usual

file mem_file: text;

set_up_the_file: process
variable L: line;
variable status: file_open_status;
begin
loop -- keep going until user gives me a valid file
write(L, string'("Please type in the filename:"));
writeline(OUTPUT, L); -- send prompt to console
readline(INPUT, L); -- get user response
-- assume it's just a filename, nothing else
file_open(status, mem_file, L.all, READ_MODE);
exit when status=open_ok; -- we're done if the file was valid
write(L, string'("Bad filename "
& L.all
& " please try again!"));
writeline(OUTPUT, L);
end loop;
-- Here when we opened the file successfully. Our work is done.
wait;
end process;

Usually, though, it's far better to sort out the filename using
a Tcl script (which can search directories, check file permissions,
invent interesting filenames and suchlike) and then use the same
script to launch the sim with an appropriate file-name generic.

HTH
--
Jonathan Bromley, Consultant

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are not the views of Doulos Ltd., unless specifically stated.

[Pontus]

You can also use environment variables when opening a file.
I've succeded both with aldecs and mentors vhdl simulators,
use $$MY_ENV_VAR for riviera, use $MY_ENV_VAR for modelsim.

So something similar to this should work (can' test my self right now)
file_open(status, "$$MY_PATH/my_file.ext", L.all, READ_MODE);

HTH -- Pontus

[Andy]

If the file is opened/read dynamically in a process, then you cannot
initialize the memory array via its declaration. With a generic, you
can initialize the array declaration with a function call that uses
the generic, opens the file, reads the data and returns an initialized
array. This initialization is done during the VHDL elaboration phase,
which is "hidden" at the beginning of many simulators (before the
actual simulation starts), but is an explicit step on others (e.g.
Cadence).

Andy

[logic_guy]

I've also written testbenches that pause and wait for the user to source
a tcl script. The tcl script sets a VHDL variable (using the "change"
command in Modelsim), issues a "force" command on a signal to trigger an
event, and that starts a process that does some massaging of the
variable (mainly to determine to number of non-blank characters) and
feeds that to a VHDL open statement to open the requested file.

Charles Bailey