need VHDL code for N bit decoder
Teoh Giap Seng
--
Hi all,
i am a newbie learning VHDL. I am trying to write a code for decoder.
Attached is my source code.
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODm2 IS
PORT
(SOURCE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
SOU : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DECODm2;
ARCHITECTURE DEC OF DECODm2 IS
BEGIN
PROCESS (SOURCE)
BEGIN
SOU <="11111111";
IF SOURCE="000" THEN SOU(0)<='0';
ELSIF SOURCE="001" THEN SOU(1)<='0';
ELSIF SOURCE="010" THEN SOU(2)<='0';
ELSIF SOURCE="011" THEN SOU(3)<='0';
ELSIF SOURCE="100" THEN SOU(4)<='0';
ELSIF SOURCE="101" THEN SOU(5)<='0';
ELSIF SOURCE="110" THEN SOU(6)<='0';
ELSIF SOURCE="111" THEN SOU(7)<='0';
END IF;
END PROCESS;
END DEC;
Currently it is a 3 bit decoder.
I am wondering if i can declare
GENERIC
(BusWidth:integer:=n)
);
And can later make my code 10 a N bit decoder. Is it possible to do so?
Lars Mathisson
For I in 0 to XXX loop
if source = i then SOU(i) <='0';
else SOU(i) <='1';
end if;
end loop;
Remeber that the input must be declared as integer for this to work.
Lars
"Teoh Giap Seng" <utm...@tm.net.my> wrote in message
news:8u5t3e$10m$1...@news.utm.my...
Charles Elias
conversion package that has more in it than the one function needed for
the decoder. I have tested this for several cases; all with N = 2**M
which is the way I would normally use it.
Best regards,
Charles
========================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------------
package Conversion is
constant ZVec : std_logic_vector( 0 to 1 ) := (others => '0');
constant ZBVec : bit_vector( 0 to 1 ) := ( others => '0' );
function INTEGER_TO_SLV (ARG, SIZE: NATURAL) return std_logic_vector;
function INTEGER_TO_BITVEC (ARG, SIZE: NATURAL) return bit_vector;
function SLV_TO_INTEGER( ARG: std_logic_vector ) return INTEGER;
function Unsigned_To_SLV( ARG : unsigned ) return std_logic_vector;
function SLV_To_Unsigned( ARG : std_logic_vector ) return unsigned;
end Conversion;
------------------------------------------------------------------------
package body Conversion is
function INTEGER_TO_SLV (ARG, SIZE: NATURAL) return std_logic_vector is
variable RESULT : std_logic_vector( SIZE - 1 downto 0 );
variable I_VAL : NATURAL := ARG;
begin
if ( SIZE < 1 ) then return ZVec;
end if;
for I in 0 to RESULT'LEFT loop
if ( I_VAL mod 2 ) = 0 then
RESULT( I ) := '0';
else RESULT( I ) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not( I_VAL =0 ) then
assert false
report "INTEGER_TO_SLV: vector truncated"
severity WARNING;
end if;
return RESULT;
end INTEGER_TO_SLV;
------------------------------------------------------------------------
function INTEGER_TO_BITVEC (ARG, SIZE: NATURAL) return bit_vector is
variable RESULT : bit_vector( SIZE - 1 downto 0 );
variable I_VAL : NATURAL := ARG;
begin
if ( SIZE < 1 ) then return ZBVec;
end if;
for I in 0 to RESULT'LEFT loop
if ( I_VAL mod 2 ) = 0 then
RESULT( I ) := '0';
else RESULT( I ) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not( I_VAL =0 ) then
assert false
report "INTEGER_TO_SLV: vector truncated"
severity WARNING;
end if;
return RESULT;
end INTEGER_TO_BITVEC;
------------------------------------------------------------------------
function SLV_TO_INTEGER( ARG: std_logic_vector ) return INTEGER is
variable result: INTEGER;
begin
assert ARG'length <= 31
report "ARG is too large in SLV_TO_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
if ARG(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end;
-----------------------------------------------------------------------
function Unsigned_To_SLV( ARG : unsigned ) return std_logic_vector is
variable result : std_logic_vector( ARG'range );
begin
for i in ARG'range loop
if ARG( i ) = '1' then
result( i ) := '1';
else
result( i ) := '0';
end if;
end loop;
return result;
end;
-----------------------------------------------------------------------
function SLV_To_Unsigned( ARG : std_logic_vector ) return unsigned is
variable result : unsigned( ARG'range );
begin
for i in ARG'range loop
if ARG( i ) = '1' then
result( i ) := '1';
else
result( i ) := '0';
end if;
end loop;
return result;
end;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
end Conversion;
=======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.conversion.all;
entity M_to_N_decode is
generic( M : positive;
N : positive );
port ( data : in std_logic_vector( M - 1 downto 0);
enable : in std_logic := '1';
dec : out std_logic_vector( N - 1 downto 0));
end M_to_N_decode;
architecture archdecode of M_to_N_decode is
begin
A: for i in 0 to N - 1 generate
dec( i ) <= '1' when ((enable = '1') and (INTEGER_TO_SLV( i,
data'length ) = data )) else '0';
end generate;
end archdecode;
--
What we hope ever to do with ease, we must first learn to do with
diligence." -- Johnson (1709-1784)
Sent via Deja.com http://www.deja.com/
Before you buy.
Mike Treseler
. . .
> I have included a
> conversion package that has more in it than the one function needed for
> the decoder.
> ========================================================================
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use ieee.numeric_std.all;
> ------------------------------------------------------------------------
> package Conversion is
-- Note that the numeric_std package referenced above already
-- includes equivalent conversion functions.
-- Here's how your example would look using the
-- standard functions:
----------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity M_to_N_decode is
generic( M : positive := 5;
N : positive := 32);
port ( data : in unsigned( M - 1 downto 0);
enable : in std_logic := '1';
dec : out std_logic_vector( N - 1 downto 0));
end M_to_N_decode;
architecture archdecode of M_to_N_decode is
begin
A: for i in 0 to N - 1 generate
dec( i ) <= '1' when ( (enable = '1')
and (to_unsigned( i,data'length ) = data )
)
else '0';
end generate;
end archdecode;
------------------------------------
-- mike.treseler at flukenetworks dot com