Hi Patel,
Ok, here goes with my interpretation of the rules that matter for this case (from VHDL-2002 LRM):
10.1 "In addition to the above declarative regions, there is a root declarative region, not associated with a portion
of the text of the description, but encompassing any given primary unit. At the beginning of the analysis of a
given primary unit, there are no declarations whose scopes (see 10.2) are within the root declarative region."
So this is saying that when starting to parse a VHDL file, the root declarative region has no declarations. Seems pretty obvious. But this is supposed to apply to primary units - but how does the compiler know if it's looking at a primary or secondary unit until it has successfully parsed part of it? Surely this applies to all design units, primary & secondary.
It says in 11.2:
"Every design unit except package STANDARD is assumed to contain the following implicit context items as
part of its context clause:
library STD, WORK ; use STD.STANDARD.all ;"
So this is how the predefined stuff gets into the root declarative region and is visible. Before the compiler gets to parsing any VHDL code, even context clauses, the root declarative region has only the following visible in it: std (library), work (library) and everything in std.standard.* . Notably, this does not include any entities of the work library such as entity 'e' from my example.
I believe that if a VHDL file has multiple design units, whether primary or secondary, parsing of each design unit begins with a fresh new root declarative region with nothing in it except the predefined stuff. So after 'end entity;' of my example, the compiler begins a fresh new root declarative region (not containing 'e').
I haven't found any special case treatment of the entity_name of an architecture body in the LRM, so I conclude that in a literal interpretation of the rules, you should actually need
architecture a of work.e is -- OK: 'e' visible by selection
...
begin
...
end architecture;
OR
use work.e;
architecture a of e -- OK: 'e' made visible by use clause
...
begin
...
end architecture;
I guess that in most VHDL compilers, there is a special case where the entity_name lookup for an architecture body is not done within the root declarative region but instead goes to the library declarative region (which certainly does have 'e' visible). The library declarative region is mentioned in a couple of places in the LRM and nowhere else, so it's not exactly obvious what its purpose is or why the LRM even mentions it.