force signals in VHDL

[esperan]

I would like to force a signal in VHDL. I know I can use TCL API in
Modelsim to do this. In fact this is exactly what I have been doing.

when -label label3 "($clk'EVENT AND $16clk = '1')" {
....
force -freeze $dummy_signal 16#[lindex $dummy_data_list 0] 0 ns,
10 ns
....
nowhen label3}

This works fine when there is only a few values that should be forced
(using several when...nowhen). But now I have a file with several
thousands of data that should be forced on to the $dummy_signal (every
clk cycle). I have tried to use one "when...nowhen" in a loop but
Modelsim just seems to get stuck and I have force the simulator to an
end.

Does someone have a solution for this problem?

[HT-Lab]

"esperan" <conn...@gmail.com> wrote in message
news:c59c8c0d-125f-4c6a...@c26g2000prf.googlegroups.com...

I would use Signalspy in my testbench.

process
begin
signal_force("/testbench/i0/i2/enable", "1",0 ns,freeze, OPEN,1);
....
end process;

FYI, VHDL2008 will support hierarchical references and has a build-in
force/release command, just log an ER with Mentor to get support for it.

Hans.
www.ht-lab.com

[KJ]

"esperan" <conn...@gmail.com> wrote in message
news:c59c8c0d-125f-4c6a...@c26g2000prf.googlegroups.com...

Write testbench code...that is simply additional VHDL code that
- Instantiates the thing you're trying to test.
- Models the input signals with VHDL code
- Checks the output signals to validate that the thing under test is working

KJ

[esperan]

On Mar 31, 11:25 am, "HT-Lab" <han...@ht-lab.com> wrote:
> "esperan" <conny...@gmail.com> wrote in message

> Hans.www.ht-lab.com- Hide quoted text -
>
> - Show quoted text -

I probably should have mentioned that I would rather not add extra
code to the testbench, but to my testcase (which is separate files in
C and Tcl) instead. But this is not really a problem now, since I have
another solution. Although it was interesting to hear that VHDL2008
will support force/relese.

/Conny