Convert time to string for textio?
Pamm
Jonathan Bromley
writes
>How can I solve this problem?
Two different answers.
1) Why bother? std.textio has a version of WRITE that will correctly
format a time value into the appropriate string.
use std.textio.all;
...
variable L: line;
variable T: time;
...
write(L, string'("The delay was "));
write(L, T);
...
2) If you have VHDL-93, use the 'IMAGE attribute:
time'IMAGE(T) is exactly the string representation of T.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan...@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Allan Herriman
>How can I solve this problem?
I'm not sure what you mean. Perhaps this would help:
use std.textio.all;
...
signal result : time;
...
whatever : process
file rpt : text open write_mode is "filename";
variable L : line;
begin
write(L, result);
writeline(rpt, L);
wait;
end process whatever;
Regards,
Allan.
VhdlCohen
>
> time'IMAGE(T) is exactly the string representation of T.
types.
But for vectors, the image and heximage overloaded functions at my site are
practical.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
Allan Herriman
>>2) If you have VHDL-93, use the 'IMAGE attribute:
>>
>> time'IMAGE(T) is exactly the string representation of T.
>That's a good solution for discret objects like time, integers, enumerated
>types.
>But for vectors, the image and heximage overloaded functions at my site are
>practical.
Hi Ben,
Your package uses access types, and therefore won't work for
synthesis.
Would you consider addressing this issue?
Converting types to strings *does* have a use in synthesis. Here's an
example from some recent code I wrote (which may look familiar if
you've seen any of Ray Andraka's posts to news:comp.arch.fpga) :
constant rloc_str0 : string := "X" & itoa(0) & "Y" & itoa((i / 2);
attribute RLOC of u1 : label is rloc_str0;
...
u1 : ...
BTW, This allows placement information to be passed through to the
back end tools.
The function itoa does the same thing as integer'image. I would have
used integer'image if it was available. Synplicity tell me it will be
working in release 7.1 of Synplify. I don't know if any other
synthesis tools support it.
Here's how I made the itoa function return a variable length string
without using access types. (This has been tested with Synplify.)
-- convert an integer to a string
-- (fails on 16#80000000#, but that's not a valid integer :-)
pure function itoa (i : in integer) return string is
constant base : positive := 10;
type look_up is array (0 to base - 1) of character;
constant itoch : look_up :=
('0','1','2','3','4','5','6','7','8','9');
constant max_int_length : positive := 21; -- big enough for 64 bit
int.
variable result : string(1 to max_int_length);
variable negative : boolean := i < 0;
variable number : integer;
variable cursor : positive := max_int_length + 1;
begin
if negative then
number := -i;
else
number := i;
end if;
loop
cursor := cursor - 1;
result(cursor) := itoch(number mod base);
number := number / base;
exit when number <= 0;
end loop;
if negative then
cursor := cursor - 1;
result(cursor) := '-';
end if;
return result(cursor to max_int_length);
end itoa;
Regards,
Allan.
Ray Andraka
Here is my itoa function. It is specifically for doing the RLOCs, so I limit it
to 3 digits. I also allow negative values since you can now
use negative offsets in RLOCs as long as there are no negatives at the top of
the hierarchy (makes the upside-down coordinates more palatable). I also use a
similar function for converting integers into the bit_vectors and hex strings
needed to initialize SRL16's, LUTs, and CLB_RAM. This also works with
synplify. It would be nice if the synth's did support 'image. I think Leo
does, but AFAIK, that is the only one. My other "wish they would support it" is
support for type real for generation of constants, for example if I want a rom
with sine values, it would be nice to use math_real to generate the sine values
to assign to a constant array. Obviously reals can't be synthesized, but I
don't see why they couldn't be used in the production of integer or s.l.v.
compile time constants.
function itoa (int: integer) return string is
constant max:natural:=3;
type table is array (0 to 9) of string (1 to 1);
constant LUT: table := ("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str:string(max downto 1);
variable ptr:natural:=0;
variable neg:boolean;
variable residue: natural;
begin
if int<0 then
residue:=-int;
neg:=true;
ptr:=1;
elsif int=0 then
str(1 downto 1):="0";
neg:=false;
ptr:=2;
else
residue:=int;
neg:=false;
ptr:=1;
end if;
while residue>0 loop
str(ptr downto ptr):=LUT(residue mod 10);
ptr:=ptr+1;
residue:=residue/10;
end loop;
if neg then
str(ptr downto ptr):="-";
ptr:=ptr+1;
end if;
return str(ptr-1 downto 1);
end itoa;
Allan Herriman wrote:
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
VhdlCohen
Thanks for pointing this out. I was thinking of testbenches, and not of
synthesis.
I suppose that you would use this conversion to attach different attributes to
components instantiated with the "generate" statement, where I is the loop
variable of the generate:
x: for i in 1 to 10 generate
constant rloc_str0 : string := "X" & itoa(0) & "Y" & itoa((i / 2);
attribute RLOC of u1 : label is rloc_str0;
U1: comp( ...)
end generate x;
Thanks for sahring the info.
Ben
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
Allan Herriman
Hi Ben,
>Allan,
>Thanks for pointing this out. I was thinking of testbenches, and not of
>synthesis.
>I suppose that you would use this conversion to attach different attributes to
>components instantiated with the "generate" statement, where I is the loop
>variable of the generate:
>x: for i in 1 to 10 generate
> constant rloc_str0 : string := "X" & itoa(0) & "Y" & itoa((i / 2);
> attribute RLOC of u1 : label is rloc_str0;
> begin
> U1: comp( ...)
>end generate x;
Exactly right.
I was placing a carry chain and related components in a xilinx part
for a thermometer code to 1-hot converter (i.e. a priority encoder).
It's the sort of thing that synthesisers don't infer very well, so I
had to instantiate the low level primitives and use attribututes to
give them the correct relative locations.
Regards,
Allan.
Allan Herriman
>Allan,
>
>Here is my itoa function. It is specifically for doing the RLOCs, so I limit it
>to 3 digits. I also allow negative values since you can now
>use negative offsets in RLOCs as long as there are no negatives at the top of
>the hierarchy (makes the upside-down coordinates more palatable). I also use a
>similar function for converting integers into the bit_vectors and hex strings
>needed to initialize SRL16's, LUTs, and CLB_RAM. This also works with
>synplify. It would be nice if the synth's did support 'image. I think Leo
>does, but AFAIK, that is the only one.
Hi Ray,
Synplify has had integer'image since 7.0.1.
Synplicity support have told me that it will be working correctly in a
future release.
Regards,
Allan.
Pamm
Pamm wrote in message ...
Tim
Here is an even smaller itoa, and not limited to 3 digits...
-------------------------------------------------------------------------
type TStr10 is array (0 to 9) of string(1 to 1);
constant Str10: TStr10 := ("0","1","2","3","4","5","6","7","8","9");
-- itoa is used in RLOC/LOC generation
function itoa( x : integer ) return string is
variable n: integer := x;
begin
if n < 0 then
return "-" & itoa(-n);
elsif n < 10 then
return Str10(n);
else
return itoa(n/10) & Str10(n rem 10);
end if;
end function itoa;
-------------------------------------------------------------------------
"Ray Andraka" <r...@andraka.com> wrote in message
news:3C477951...@andraka.com...
Allan Herriman
<t...@rockylogic.com.nooospam.com> wrote:
>Ray
>
>Here is an even smaller itoa, and not limited to 3 digits...
>
> -------------------------------------------------------------------------
> type TStr10 is array (0 to 9) of string(1 to 1);
> constant Str10: TStr10 := ("0","1","2","3","4","5","6","7","8","9");
> -- itoa is used in RLOC/LOC generation
> function itoa( x : integer ) return string is
> variable n: integer := x;
> begin
> if n < 0 then
> return "-" & itoa(-n);
> elsif n < 10 then
> return Str10(n);
> else
> return itoa(n/10) & Str10(n rem 10);
> end if;
> end function itoa;
> -------------------------------------------------------------------------
This is likely to crash the simulator or synthesiser if ever passed
the (evil) number 16#80000000# (i.e. integer'low) because the thing
gets stuck, recursively calling itself until it runs out of memory.
Most VHDL tools on 32 bit platforms use 32 bit twos comp arithmetic,
and -(16#8000000#) is 16#80000000#
The function I posted will produce the wrong output when given this
argument, but it won't crash the tool. I'm not sure which is worse:
crashing, or giving the wrong answer. The ideal implementation would
do neither of course.
Regards,
Allan.
Ray Andraka
Tim wrote:
--
Tim
if n < ..... then
report "too big (negative)";
return "error"
elsif n > ..... then
report "too big (positive)";
return "error"
elsif n < 0 then
....
"Allan Herriman" <allan_herriman.hates.spam@agil....com> wrote
Allan Herriman
<t...@rockylogic.com.nooospam.com> wrote:
>Thanks Alan. I guess the first lines become
>
>if n < ..... then
> report "too big (negative)";
> return "error"
>elsif n > ..... then
> report "too big (positive)";
> return "error"
>elsif n < 0 then
> ....
The hard part is filling in those "....." parts. You can't put a
fixed number (like 2147483647) there because you don't know if you are
running on a 32 bit machine.
Of course, you could test for that, but the function is starting to
get a little unwieldy.
Maybe ...
if integer'low = - integer'low then
-- we are on a twos comp machine
-- so trap the fault condition
if n <= integer'low then
report "too big (negative)";
return "error";
...
Regards,
Allan.
bk...@hotmail.com
First call the text library:
use STD.textio.all;
use IEEE.STD_LOGIC_TEXTIO.all;
In the process declare a line variable like this:
variable my_line : line;
Now you can print in your code. Here is an example:
write(my_line, string'(" HMASTER_q "));
STD.textio.hwrite(my_line, HMASTER_q);
write(my_line, string'(" at "));
write(my_line, now);
writeline(output, my_line);
taken from bknpk vhdl
http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_print_debug_tip.html