VHDL 'Generate' construct - Verilog equivalent ??
Ron
functionality of the VHDL 'Generate' construct in Verilog. I need to use
generate loops and conditional generates, all of which are controlled by model
parameters (generics in VHDL).
Not being a Verilog expert, I don't know how to get around this one.
To preempt any 'smart' replies as to why I need to use Verilog, lets just say
that it's very important.
I appreciate all positive replies.
Ronnie.
Himanshu M. Thaker
Ron <rw.c...@ee.qub.ac.uk> wrote:
>Can anyone tell me (from experience or otherwise) if I can capture the
>functionality of the VHDL 'Generate' construct in Verilog. I need to use
>generate loops and conditional generates, all of which are controlled by model
>parameters (generics in VHDL).
There is no build in way to use a true VHDL generate
statement. However, you can use a macro preprocessor to get
around this problem. There is a tool that does this...
contact the following person for more information...
(Disclaimer : I am part owner of Vtools Inc.)
Eric Dormer
President, Vtools Inc.
245 Spruce Ridge Rd.
RR# 2, Carp, Ontario,
Canada KOA 1L0
e-mail: vto...@sonetis.com fax: (613)-836-4579
phone: (613)-836-4466
>Ronnie Craig,
Hemi
---------------------Above opinions are my own-----------------------------
Hemi Thaker Fujitsu Network Transmission Systems Ph.: (214) 479-3739
Senior Hardware 2801 Telecom Parkway Fax: (214) 479-6989
Engineer Richardson, Texas, 75082 hmth...@tddcae99.fnts.com
--
---------------------Above opinions are my own-----------------------------
Hemi Thaker Fujitsu Network Transmission Systems Ph.: (214) 479-3739
Senior Hardware 2801 Telecom Parkway Fax: (214) 479-6989
Engineer Richardson, Texas, 75082 hmth...@tddcae99.fnts.com
Janick Bergeron
Ron <rw.c...@ee.qub.ac.uk> wrote:
>Can anyone tell me (from experience or otherwise) if I can capture the
>functionality of the VHDL 'Generate' construct in Verilog. I need to use
>generate loops and conditional generates, all of which are controlled by model
>parameters (generics in VHDL).
Your can sort-of emulate the for-generate statement using the iterated
instance construct. But that's a new feature included in the IEEE standard
and most simulator do not support it (yet). I have never used it. Unlike
VHDL's for-generate which can be used to replicate any concurrent statement,
Verilog's iterated instances can only be used to replicate instances of the
same module.
The only way you can emulate the if-generate is by using the
preprocessor `ifdef/`else/`endif/`define/`undef structure but they
can't be controlled via parameters, only from the command-line. To get
a parameter-controlled if-generate equivalent will necessitate using a
behavioral if statement and explicitely code it as behavior.
Unfortunately, it cannot be used to control instantiations.
As a general rule, you can model anything in either language, but that
does not mean that it is approached the same way. Maybe you need to
redesign your model architecture to better fit a Verilog implementation
but that it difficult to say without more details.
--
Janick Bergeron Qualis Design Corporation Ph.: (503) 531-0377
Director of PO Box 4444 Fax: (503) 629-5525
Technology Beaverton, OR, USA, 97075-4444 jan...@qualis.com
VHDL - Verilog - Synthesis - Modelling - Verification - Training
Bernd Paysan
> In article <1995Sep13....@queens-belfast.ac.uk>,
> Ron <rw.c...@ee.qub.ac.uk> wrote:
> >Can anyone tell me (from experience or otherwise) if I can capture the
> >functionality of the VHDL 'Generate' construct in Verilog. I need to use
> >generate loops and conditional generates, all of which are controlled by model
> >parameters (generics in VHDL).
>
> Your can sort-of emulate the for-generate statement using the iterated
> instance construct. But that's a new feature included in the IEEE standard
> and most simulator do not support it (yet). I have never used it. Unlike
> VHDL's for-generate which can be used to replicate any concurrent statement,
> Verilog's iterated instances can only be used to replicate instances of the
> same module.
Yes, IMHO the 'generate' statement is missing in Verilog, and an iterated
instance construct isn't nearly as flexible. The IEEE standard team should
rather implement a if ... generate statement. Using a preprocessor isn't
really what is needed. One example would be a carry select adder, which
could be (recursively) described (parameter l is the input length) about as:
if (l<2) generate
assign { cout1, sout1 } = in1 + in2,
{ cout2, sout2 } = in1 + in2 + 1'b1;
else generate
// declare some wires
add #(l/2) addhi (in1[1:l/2], in2[1:l/2], south1, couth1, south2, couth2);
add #(l-l/2) addlo (in1[l/2+1:l], in2[l/2+1:l], soutl1, coutl1, ...);
assign { cout1, sout1} = { coutlo1 ? {couth2, south2} : {couth1, south1},
soutl1 };
assign { cout2, sout2} = { coutlo2 ? {couth2, south2} : {couth1, south1},
soutl2 };
end
> The only way you can emulate the if-generate is by using the
> preprocessor `ifdef/`else/`endif/`define/`undef structure but they
> can't be controlled via parameters, only from the command-line. To get
> a parameter-controlled if-generate equivalent will necessitate using a
> behavioral if statement and explicitely code it as behavior.
> Unfortunately, it cannot be used to control instantiations.
Yes, but instantiation is important, because Verilog functions don't have
parameters (and thus can not replace modules). IMHO, VHDL's generate
statement is elegant enough to include a complete equivalent into
future Verilog implementations. Next task: write a generic multiplier
array (parameters w and h) that generates all the nessecary 3:2 adder
instanzes, and declares all the needed conections ;-).
--
Bernd Paysan
"Late answers are wrong answers!"
http://www.informatik.tu-muenchen.de/~paysan/