** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ps Iteration: 1 Instance: /testbench/inst1/instsub1
I always activate the Reset signal in the beginning. Before the reset
has any effect some of the signals are uninitialized and cause the
above warning. How do I get rid of this.
Thanks in advance.
Tom
If the warning comes from the test bench side assign your signals
initial values. It does not matter if your signals are registered or
not you can always assign an initial value. I run into similar
problems with signals that were driven by combinatiorial
logic. Assigning an initial values made warnings go away and did not
affect simulation results because proper values were assigned by logic
rigth after reset. You can do that also with code that you are going
to synthesize but then your synthesis tool is likely to warn you about
that.
set IgnoreWarning 1
After few ns do
set IgnoreWarning 0
(You could also put the above sequence to a tcl script and load it
automatically every time).
HTH,
Srinivasan
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India
I don't speak for Intel
"Tom Verbeure" <tom.ve...@verizon.no.sp.am.net> wrote in message
news:XqgL8.7021$Oj4....@nwrddc03.gnilink.net...
Hi
This is only a warning, you can safely ignore it. It just means that your signal
are not initialized, which is quite normal at 0ps.
You can assign an initial value to your signals (which may cause a synthesis
warning) to get rid of this simulation warning.
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