Stopping the simulation in Modelsim Altera Starter Edition/Linux?

[Petter Gustad]

I usually finish my simulations from a tcl script this way:

when -label end_of_simulation {end_of_simulation == true} {echo "End of simulation"; quit;}

And in the top level of my testbench I have

signal end_of_simulation : boolean := false;
...
assert not (signature = G_FINALVAL) report "test status: passed :" severity note;
end_of_simulation <= true;

This works fine under Windows, but in ASE/Linux it will simply say:

# End of simulation
# Break key hit

and then just sit there forever until i kill it. Interrupting it with
C-c does not even work, I have to kill the process. Is this a bug or a
feature? How do you stop the SE version under Linux?

Petter
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[David Bishop]

Petter Gustad wrote:

> And in the top level of my testbench I have
>
> signal end_of_simulation : boolean := false;

This depends on your simulator, but in Modeltech, I do the following:

signal stop_clock : boolean := false;
signal clk : std_ulogic;

-- purpose: clock driver
clkprc: process is
begin -- process clkprc
if (not stop_clock) then
clk <= '0';
wait for clock_period/2.0;
clk <= '1';
wait for clock_period/2.0;
else
wait;
end if;
end process clkprc;

When I am done, I set "stop_clock" to true, that turns off the clock.
Since there is no more activity (nothing for the scheduler to schedule),
that stops the simulation.

Another thing you can do is this:
assert "END OF SIMULATION" severity fatal;
It will give you an error, but it will end your sim in any simulator.

In VHDL-2008, you can just do this:

use ieee.env.all;

finish(0);

[Petter Gustad]

David Bishop <dbi...@vhdl.org> writes:

> This depends on your simulator, but in Modeltech, I do the following:
>
> signal stop_clock : boolean := false;
> signal clk : std_ulogic;
>
> -- purpose: clock driver
> clkprc: process is
> begin -- process clkprc
> if (not stop_clock) then
> clk <= '0';
> wait for clock_period/2.0;
> clk <= '1';
> wait for clock_period/2.0;
> else
> wait;
> end if;
> end process clkprc;
>
>
> When I am done, I set "stop_clock" to true, that turns off the clock.
> Since there is no more activity (nothing for the scheduler to
> schedule), that stops the simulation.
>
> Another thing you can do is this:
> assert "END OF SIMULATION" severity fatal;
> It will give you an error, but it will end your sim in any simulator.

I've tried this (I assume you mean severity failure, which is what the
testbench does in the case the self-check fails), but it takes me back
to the vsim prompt and halts, which seem to be different behaviour
than PE on Windows.

However, stopping the clock to run out of events make it exit like I
want to. Thanks!

I also figured out that redirecting stdin from /dev/null will cause it
to exit the severity failure case as well:

vsim -c tb_whatever -do batch.do < /dev/null

> In VHDL-2008, you can just do this:
>
> use ieee.env.all;
>
> finish(0);

Yes, sort of what I've been doing in Verilog for the past 20 years...