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Fifo in VHDL (on Virtex)

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Marc Reinert

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Apr 5, 2000, 3:00:00 AM4/5/00
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Has anybody an effektive VHDL-Code to implement a FIFO in a Virtex FPGA?

I konw that there are some application notes on the Xilinx webpage. But
I didn't find VHDL examples.
I need an asynchronous FIFO, min. 70 MHz, only on Bit width. How can I
use the special RAM-features of the Virtex?

Maybe somebody has used such a FIFO and can send me some information.

Thank U

Marc


Thomas Hellerforth

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Apr 6, 2000, 3:00:00 AM4/6/00
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Hi Marc,
you can use the "Xilinx Core Generator" to generate a RAM-model in VHDL.
Realizing a FIFO, I would suggest the Dual-Ported-RAM with Port A as a
Data-Input
and Port B as a Data Output.


Marc Reinert schrieb:

best regards
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Jamil Khatib

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Apr 6, 2000, 3:00:00 AM4/6/00
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check My FIFO design at
http://www.geocities.com/SiliconValley/Pines/6639/ip/fifo.html

Jamil Khatib
OpenIP Organization http://www.openip.org

Gardiner, Charles

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Apr 14, 2000, 3:00:00 AM4/14/00
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... or take a look at our offering under

http://www.atd.siemens.de/it-dl/eda/
and then click on 'ASIC & FPGA Design' on the left. A label 'asynchronous FIFO' will
then appear from which you can download the VHDL sources.
The solution uses two indepentently clocked Flipflops to guard each cell and is
probably not very suitable for deep FIFOs since each storage location costs you an
overhead of two flip-flops.
Our approach for deep FIFOs between asynchronous blocks is to cascade a shallow
asynchronous FIFO (up to sixteen location usually) and a deeper synchronous one,
which is much cheaper to implement.

Regards,
Charles

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