Verilog Binary Divider

[Kristo Godari]

I need a Verilog behavioral model (verilog behavioral code) for:
- unsigned 8-bit division

The module I have to use is this one:

module divider(
output reg[7:0] q,
output reg[7:0] r,
input [7:0] a,b);
endmodule

where a=b*q+r

Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms
to solve it.

Can someone help me?

[alb]

Hi Kristo,

why not posting on comp.lang.verilog? this is a vhdl newsgroup.

About cross-posting I also have some comments: try to avoid it if at all
possible and if necessary try to mention that you crossposted the
message on another group so that people might be able to track and post
accordingly.

On the particular subject (even if does not make a difference if it is
verilog or vhdl), I would try to understand what is the peculiarity of
each algorithm and which of these benefits and costs is more suited to
your application. Google is your friend here, a first search brings up a
lot of stuff on power awareness, speed, and also some models (opencores).

Another possibility is to implement them all and then pick up the one
that performs better in your particular application. I usually tend to
use comparison when it comes to performances optimization, but only if
the gain is worth the pain!

HTH,

Al

[Nikolaos Kavvadias]

Hi Kristo

Why not assess the offers you have in freelancer? Some offers may guarantee quality work with good quality/$ balance for you.

Best regards
Nikolaos Kavvadias