Is it possible to get back the ".vhd" file which is annotated with
delay values coming from the SDF file?
Now:
...
q_OBUF_D2 : X_AND2
port map (
I0 => a,
I1 => b,
O => q );
...
After that
...
q_OBUF_D2 : X_AND2
generic map (
tipd_I0 => (10.000 ns, 10.000 ns),
tipd_I1 => (10.000 ns, 10.000 ns),
tpd_I0_O => (10.000 ns, 10.000 ns),
tpd_I1_O => (10.000 ns, 10.000 ns)
)
port map (
I0 => a,
I1 => b,
O => q
);
...
Thanks
Tools usually can spit out a .VHO file which is VHDL of the final
mapped design. Check the docs for the tool you're using on how to
enable this output file.
KJ