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VHDL code for integrator

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Harry Yang

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Jan 24, 2000, 3:00:00 AM1/24/00

Hi, I have a problem about VHDL coding. Could anyone give me a hand?
Really appreciated.
The problem is as follows:
I have a VHDL code for integrator:

signal stage1_tmp: std_logic_vector;
signal stage1_out: std_logic_vector;
...
stage1_tmp <= ADD(stage1_out,data_in);
process(CLK,RESET)
begin
if RESET='0' then
if (CLK'event and CLK='0') then
stage1_out <= stage1_tmp;
end if;
else
stage1_out <= (others=>'0');
end if;
end process;

the code is simple, but the value of stage1_tmp can not be transferred
to stage1_out. I don't know why.
thank you for your time.
harry

Rémi SEGLIE

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Jan 25, 2000, 3:00:00 AM1/25/00

Hi,

I think the best to write is :

process(CLK,RESET)
begin
if RESET='1' then

stage1_out <= (others=>'0');

elsif (CLK'event and CLK='0') then

stage1_out <= stage1_tmp;
end if;

end process;

"Harry Yang" <hay...@doe.carleton.ca> a écrit dans le message news:
388D0219...@doe.carleton.ca...

charle...@my-deja.com

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Jan 25, 2000, 3:00:00 AM1/25/00

In article <388D0219...@doe.carleton.ca>,

Harry Yang <hay...@doe.carleton.ca> wrote:
> Hi, I have a problem about VHDL coding. Could anyone give me a hand?
> Really appreciated.
> The problem is as follows:
> I have a VHDL code for integrator:
>
> signal stage1_tmp: std_logic_vector;
> signal stage1_out: std_logic_vector;
> ...
> stage1_tmp <= ADD(stage1_out,data_in);
> process(CLK,RESET)
> begin
> if RESET='0' then
> if (CLK'event and CLK='0') then
> stage1_out <= stage1_tmp;
> end if;
> else
> stage1_out <= (others=>'0');
> end if;
> end process;
>
> the code is simple, but the value of stage1_tmp can not be transferred
> to stage1_out. I don't know why.
> thank you for your time.
> harry
>
>

Harry,

The only problem I can see is that stage1_tmp should be in the
sensitivity list of the process. One compiler I use will give a
warning about this, another gives no warning, but the code will not
simulate properly.

Charles.

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Before you buy.

me...@mench.com

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Jan 25, 2000, 3:00:00 AM1/25/00

On Tue, 25 Jan 2000 11:52:08 GMT, charle...@my-deja.com wrote in
article <86k2p8$6l6$1...@nnrp1.deja.com>:

> The only problem I can see is that stage1_tmp should be in the
> sensitivity list of the process. One compiler I use will give a
> warning about this, another gives no warning, but the code will not
> simulate properly.

No, that's unnecessary--it won't change the simulation one bit,
although it might make certain synthesis tools not emit a warning.

The only time stage1_tmp gets assigned is when reset='0' and clk='0'
and clk'event, independent of whether stage1_tmp has an edge on it.
So, only reset and clk need be in the sensitivity list.

Paul

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