Newbie Help: How do you set up test benches? (using Aldec Active HDL)

[SQ 240]

Subject says it all. I need to implement a test bench for one of my graduate
classes, and we have not covered test benches. The book I have is not telling
me anything, so I need a little help. Any ideas?

Jason

"When you look into the mirror, do you like what's looking at you? Now that you
see your true reflection, what on earth are you gonna do?" -- Boyd Tinsley of
Dave Matthews Band, song: "True Reflections"

[sweir]

Jason,

Aldec let's you set-up stimulus without building a formal test bench, but
that is very limited, and I never found it of much use.

A test bench is just a model that does not have external ports and
instantiates the model(s) you are testing. At a minimum, you need to
generate a reset, a clock, and some form of test stimulus.

The clock and reset are straightforward:

architecture behave of test_bench is
...
signal clock : std_logic := '1' ;
signal reset : std_logic := '1' ;
...
begin
clock <= not( clock ) after ( CLOCK_PERIOD / 2 ) ns ; --fs, ps, ns,
us, ms etc
reset <= '0' after ( CLOCK_PERIOD / 2 ) ns ;

Here, reset asserts from 0, and negates the first time the clock falls.

In the most trivial test-benches, you just drive the DUT inputs and manually
observe the outputs. Self-checking test benches are much more thorough and
usually include transactor models that interact with the design, and a test
vector reader that reads vectors either from a constant array defined in the
test-bench, ( very fast ), or from a file, ( doesn't need recompilation of
the test bench for every test vector change ).

"VHDL" by Perry, and to a lesser extent "VHDL Primer" by Bhasker will
probably help you.

Regards,

"SQ 240" <sq...@aol.com> wrote in message
news:20020506173745...@mb-ba.aol.com...

[Neeta]

Jason,

here's a example test bench to test the working of a comparator. It
makez Z high if A > B, and 0 Otherwise.

-----

library IEEE;
use ieee.sparc0S5.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
--use IEEE.std_logic_unsigned.all;

entity TB_MULT is
generic(N:integer:=16;POW2_N:integer:=10);
end TB_MULT;

architecture LAB2_ARCH of TB_COMP is

--************************************************
-- between these comments, add your component def,
-- configuration specifications, and any signal
-- definitions for the component you are testing

component COMP is
generic(N : integer := 16);
port( A,B: in std_logic_vector(N-1 downto 0);
Z: out std_logic);
end component COMP;

for UUT: COMP use entity WORK.COMP(LAB2_ARCH);
--for UUT: B_MULT use entity WORK.B_MULT(SYN_BEHAVIORAL);

signal A_INT,B_INT : integer range -POW2_N to POW2_N-1;
signal A,B:std_logic_vector(N-1 downto 0);
signal COMPAB:std_logic;
--************************************************

begin

UUT: COMP generic map (N=>N) port map (A=>A,B=>B,Z=>COMPAB);

DRIVE:process
variable COMP_INT : std_logic;
begin
for i in POW2_N downto POW2_N-1 loop
for j in -POW2_N to POW2_N-1 loop
A_INT <= i;
B_INT <= j;
if (i < j) then
COMPAB_INT:=1;
else COMPAB_INT:=0;
end if;
wait for 5 ns;
if COMPAB /= COMPAB_INT then
assert (false) report "Error: answer wrong" severity
FAILURE;
end if;
wait for 1 ns;
end loop;
end loop;
wait for 10 ns;
assert (false) report "sim done" severity FAILURE;
end process DRIVE;

A <= conv_std_logic_vector(A_INT,N);
B <= conv_std_logic_vector(B_INT,N);

end BEHAVIORAL;
configuration TB_CONFIG of TB_COMP is
for LAB2_ARCH
end for;
end;

---

Try getting "VHDL primer - J.Bhasker"

Good luck,
-neeta

sq...@aol.com (SQ 240) wrote in message news:<20020506173745...@mb-ba.aol.com>...

[Tuukka Toivonen]

In article <20020506173745...@mb-ba.aol.com>, SQ 240 wrote:
> Subject says it all. I need to implement a test bench for one of my graduate

Why not use google? http://www.i2.i-2000.com/~stefan/vcourse/html/

[ben cohen]

Take a look at my last 2 books that address the issue of testbench
designs using transaction based approach with instructions from the
transactor either from command files (with a resuable parser), and/or
directly from VHDL transactions.

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
------------------------------------------------------------------------------

[Ray Andraka]

Aldec makes this pretty easy for you. If you click on the + next to the file name
in the design browser, it will show you the entity/architectures found in that file
underneath. Now right click on the entity-architecture you want a test bench for,
then select generate testbench from the pop-up menu. This will generate a
testbench template with the component instantiated. All you have to do then is
write some code to exercise the component. At a minimum, you'll probably need a
clock, perhaps a reset generator and a stimulus for your design. Make each of
these a separate process. There are a number of testbench examples in the aldec
tool examples, as well as material on testbenches in the on-line documentation and
help files. Take a bit of time to go through that information: there is a wealth
of good information as well as training material in the Aldec tool.

SQ 240 wrote:

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

[VhdlCohen]

>Aldec makes this pretty easy for you. If you click on the + next to the file

name .......>
For the creation of a TB template, emacs does a similar thing,
However, for TB guidelines and approaches the transaction based method has
gained popularity, and is also described in my books.