Multiple events in VHDL

[Anoop Nannra]

Hi all,

I was wondering if it is possible to have a process run on multiple
clock edges in VHDL similar to the following verilog code:

always @(posedge clk1 or posedge clk2)
:
:
:
end

TIA
Anoop

[me...@mench.com]

Anoop Nannra <"anannra"@no-spamnortelnetworks.com(remove no-spam)> wrote:
> I was wondering if it is possible to have a process run on multiple
> clock edges in VHDL similar to the following verilog code:

> always @(posedge clk1 or posedge clk2)

Yes, you can:

process
begin
wait until rising_edge( clk1 ) or rising_edge( clk2 );
:
:
end process;

Just as in the Verilog example, this process is not synthesizable.

Hope this helps,

Paul

--
Paul Menchini | me...@mench.com | "Non si vive se non il
OrCAD | www.orcad.com | tempo che si ama."
P.O. Box 71767 | 919-479-1670[v] | --Claude Adrien Helvetius
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[phil_j...@my-dejanews.com]

When you place a signal in a process sensativity list, the process is invoked
whenever that signal changes state. So, if a clock is included in a process
sensativity list, the process is executed on the rising edge and on the
falling edge. To have events happen on both edges, include two edge
statements as shown below. Note that this is not synthesizable as there is no
definition for a flip flop that can be clocked off of both edges of a clock.

rise_fall_example : process (RESET, CLOCK)
begin
if (RESET = '1') then
OUTPUT <= '0';
elsif (CLOCK'event) and (CLOCK = '1') then -- Rising Edge
OUTPUT <= INPUT1;
elsif (CLOCK'event) and (CLOCK = '0') then -- Falling Edge
OUTPUT <= INPUT2;
end if;
end process rise_fall_example;

In article <7cqtqt$75j$1...@bcarh8ab.ca.nortel.com>,

Anoop Nannra <"anannra"@no-spamnortelnetworks.com(remove no-spam)> wrote:

> Hi all,

>
> I was wondering if it is possible to have a process run on multiple
> clock edges in VHDL similar to the following verilog code:
>
> always @(posedge clk1 or posedge clk2)

> :
> :
> :
> end
>
> TIA
> Anoop
>
>

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[nav...@my-dejanews.com]

In article <7cqtqt$75j$1...@bcarh8ab.ca.nortel.com>,
Anoop Nannra <"anannra"@no-spamnortelnetworks.com(remove no-spam)> wrote:
> Hi all,
>
> I was wondering if it is possible to have a process run on multiple
> clock edges in VHDL similar to the following verilog code:
>
> always @(posedge clk1 or posedge clk2)
> :
> :
> :
> end
>
> TIA
> Anoop
>
>

Hi,
I VHDL the sensitivity list consists of only the signal names and no edges
can be given. Inside the process clk'event has to be used for both the clocks.
i.e (clk'event and clk = 1) for both the clocks.

Regards
Aravind Navada K