NOT (std_logic)

[David Peavey]

This may sound like a dumb questions but what is the easiest way
to invert an std_logic signal. I.E. I want to make

in out
'1' '0'
'0' '1'
'H' '0'
'L' '1'

and I really don't care too much about the other input values.
There appears to be a NOT function defined in the
ieee.std_logic_1164 library but it is defined for
std_logic_VECTORS. Again - I would like a SIMPLE solution.
(i.e. a one liner). I can do this with a table lookup or some
other logic but would really like to keep it simple.

signal a, b std_logic;
...
a <= NOT b; -- doesn't work
a <= not(b); -- doesn't work either

Thanks
Dave

[Klaus Falser]

In article <3727F1CD...@home.net>,

I do not know what compiler you are using, but I have no problems to
compile the following (with ModelSim):

library ieee;
use ieee.std_logic_1164.all;

entity test is

port (
a : out std_logic;
b : in std_logic);

end entity test;

architecture rtl of test is

begin -- architecture rtl

a <= NOT(B);

end architecture rtl;

The function not() is defined in std_logic_1164 with std_ulogic as parameter
and returning XU01.

Best regards
Klaus Falser
--
Klaus Falser
Durst Phototechnik AG
I-39042 Brixen

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[Renaud Pacalet]

David Peavey wrote:
>
> This may sound like a dumb questions but what is the easiest way
> to invert an std_logic signal. I.E. I want to make
>
> in out
> '1' '0'
> '0' '1'
> 'H' '0'
> 'L' '1'
>
> and I really don't care too much about the other input values.
> There appears to be a NOT function defined in the
> ieee.std_logic_1164 library but it is defined for
> std_logic_VECTORS. Again - I would like a SIMPLE solution.
> (i.e. a one liner). I can do this with a table lookup or some
> other logic but would really like to keep it simple.
>
> signal a, b std_logic;
> ...
> a <= NOT b; -- doesn't work
> a <= not(b); -- doesn't work either
>
> Thanks
> Dave

IEEE.STD_LOGIC_1164 (the one I know) contains a not function that
performs exactly as you want. And I'm talking of the IEEE version of
the package: v4.200, 01/02/92,
http://vhdl.org/vi/libutil/utilities/gen_functions/IEEE1164
What version do you use?
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pac...@enst.fr

[Le mer Michel]

David Peavey wrote:

> This may sound like a dumb questions but what is the easiest way
> to invert an std_logic signal. I.E. I want to make
>
> in out
> '1' '0'
> '0' '1'
> 'H' '0'
> 'L' '1'
>
> and I really don't care too much about the other input values.
> There appears to be a NOT function defined in the
> ieee.std_logic_1164 library but it is defined for
> std_logic_VECTORS. Again - I would like a SIMPLE solution.
> (i.e. a one liner). I can do this with a table lookup or some
> other logic but would really like to keep it simple.
>
> signal a, b std_logic;
> ...
> a <= NOT b; -- doesn't work
> a <= not(b); -- doesn't work either
>
> Thanks
> Dave

Hello

You can do :

a <= not (To_X01(b));

( Library ieee.std_logic_1164 )

Hope this helps,

Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes (France)
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm